A Leakage Compensation Design for Low Supply Voltage SRAM

Abstract

A leakage current compensation design for nanoscale SRAMs is proposed in this paper. The proposed compensation design is composed of a leakage current sensor, which generates a warning signal if the leakage is over a predefined threshold, and a compensation circuit following the sensor, which will be activated to speed up the read operation. At 0.6 V system voltage, the proposed compensation design reduces 27.86% of the average power dissipation, and 54.88% of the read delay at the expense of 3.64% area overhead. The proposed Static Random-Access Memory is implemented using the TSMC 40-nm CMOS logic technology. The energy per access is measured to be 0.9411 pJ given a 600-mV power supply and a 54-MHz system clock rate.