A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM

Abstract

A readout circuit with slew rate compensation for nano-scaled SRAMs (Static Random-Access Memory) is proposed in this study. Since the leakage current will dramatically increase to jeopardize memory read/write performance when the nano-scaled SRAM is operated at high system voltages, the proposed AVD (Adaptive Voltage Detector) is utilized to detect the system voltage variation to resolve this issue. When AVD generates an enable signal to WLBC (Word Line Boost Circuit), WLBC will boost wordline voltage to drive the SRAM cell such that the output slew rate is increased. Therefore, the active power of the SRAM will be reduced. A prototypical SRAM is implemented using TSMC 28 nm CMOS logic low power technology. By measurement results at 0.8 V system voltage, the proposed compensation design reduces 17.2% of the power dissipation, and enhances the output slew rate by 46.5% at the expense of 6.6% area overhead. The energy per access is measured to be 0.414 pJ given a 0.8 V system voltage and 100 MHz system clock.