Simulation-Based Study of High-Density SRAM Voltage Scaling Enabled by Inserted-Oxide FinFET Technology

Abstract

A scheme for precisely adjusting the drive strength of an inserted-oxide FinFET (iFinFET) comprising two nanowire (NW) channel regions that are separated by a thin oxide layer, to enhance the manufacturing yield of a minimally sized six-transistor static random access memory (6T-SRAM) cell, is investigated in this paper. The 3-D process simulations show that the upper NW channel region can be selectively rendered nonconducting by dopant ion implantation followed by thermal annealing so that its threshold voltage is greater than the supply voltage ( ${V}_{\text {DD}}$ ). Furthermore, the position of the inserted-oxide layer can be adjusted to balance the tradeoff between the read stability and write-ability to achieve the lowest minimum cell operating voltage ( ${V}_{\text {min}}$ ). Using a compact transistor model calibrated to 3-D device simulations, doped iFinFET technology is projected to enable ${V}_{\text {min}}$ of a minimally sized 6T-SRAM cell to be substantially lower than ${V}_{\text {DD}}$ , eliminating the need for write-assist circuitry and lowering power consumption.