Single-Bit Architecture for Low Power IoT Applications

Abstract

AbstractThis paper discusses how six transistor static random access memory cells work, how a write driver circuit works, and how different sense amplifiers work, like a current differential sense amplifier and a current latch sense amplifier. This paper also discusses the proposed architecture for low-power Internet of Things applications and how it works and looks. They include a six-transistor static random access memory cell, a write driver, and a variety of sense amplifiers, such as current differential and current latch sense amplifiers, that can help people Schematic out what is going on in their devices. Low-power forced stacks, low-power sleep stacks, and low-power dual sleep techniques. To make the proposed architectures more powerful, low-power designs make six transistor static random access memory cells less powerful. Using a six-transistor static random access memory cell with less power is the best way to make it work. In this case, the current latch sense amplifier in architecture uses the least amount of power, 8.34µW with 35 transistors, compared to other architectures. This is because of the area of the amplifier increases.KeywordsLow Power Reduction Techniques (LPRT)Circuit of Write Driver (CoWD)Six Transistor Static Random-Access Memory Cell (6TSRAMC)Current Differential Sense Amplifier (CDSA)Current Latch Sense Amplifier (CLSA)