Performance Analysis of Cache Memory Design for Single Bit Architecture for IoT Systems

Abstract

This paper describes the performance analysis of cache memory design for single-bit architecture. Single Bit Architecture comprised of a circuit of write driver, six transistors static random access memory cell, and sense amplifiers such as charge transfer differential sense amplifier and current latch sense amplifier. Apart from it, different parameters of architecture such as consumption of power and number of transistors have been analyzed at different values of resistance. The conclusion arises that single-bit six transistors static random access memory cell current latch sense amplifier architecture consumes 43.29$\mu$W of power with 33 transistors. This analysis has done using a cadence tool at 90$\eta$m technology at V$_{\mathbf{DD}}=$ 1.2V.