Abstract
Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations. We leverage this asymmetric property i n near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 21.45% with approximate 10.19% performance speed-up.
Highlights
Improving energy efficiency has become one of the primary objectives of current microprocessor design
Several key facts have emerged from earlier development of Near Threshold Computing (NTC) techniques so far: (1) energy efficiency compromise exists in single-supply NTC systems due to different Vopt for core and memory; (2) memory reliability limits further lowering of the supply voltage to achieve energy optimality; and (3) dual-supply architecture addresses a fundamental shortcoming of NTC’s single-thread performance through voltage boosting
The abscissa of the averaged characteristic points are increased by one to two roughly. These results suggest that our proposed Write Aggregation Buffer (WAB) and Write back aggregation buffer (WBAB) structure is able to universally improve the characteristics of long consecutive read sequence potential (LCRSP) across diverse benchmarks that could result in 10× to roughly 1000× longer read sequence for our opportunistic dual-supply switching scheme to exploit further energy savings. when we observe the LCRSP promotions of SPEC2006.401.bzip2, PARSEC.fluidanimate and PARSEC.streamcluster workload by increasing the WAB size, we discover that there should be a saturation border for each workload’s LCRSP improvement
Summary
Improving energy efficiency has become one of the primary objectives of current microprocessor design. For NTC systems with only a single digital supply (VDD), the supply voltage level is often dictated by the minimum voltage (Vmin) to ensure reliable operation of its memory blocks This requires the system to operate at a higher supply voltage than the optimal supply for the logic core, and results in sub-optimal system-level energy efficiency. Our in-depth analysis of memory reliability based on circuit-level simulation of typical six-transistor static random access memory (6T-SRAM) cells in 7 nm and 16 nm FinFET Technology processes reveals that read and write operations exhibit asymmetric behaviors at near-threshold voltages This asymmetry suggests that it is possible to operate memory read and write at different voltage levels without incurring significant performance and reliability penalty. Our method shows 21.45% improvement compared to the baseline, where a single fixed near-threshold voltage is used as the supply
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