VLSI Structures Research Articles

Titanium Disilicide Formation on Cmos Structures with Phosphorous Doped Gates

ABSTRACTSelf aligned refractory metal silicides such as titanium disilicide have been used extensively in VLSI and ULSI structures. Unlike earlier work which has relied on undoped substrates and a single implant species, in the present study TiSi2 formation on phosphorous doped poly-Si in the presence of multiple dopants has been investigated. TEM micrographs are discussed which show the difference in silicide formation for the case of the BF2 and arsenic implanted samples. We have found that the presence of fluorine in the BF2 implant retards the silicide formation for phosphorous doped poly-Si substrates. Additionally, the effect of substrate grain size on TiSi2 formation has been investigated using undoped α-Si and poly-Si substrates.

Vertical migration of software functions and algorithms using enhanced microsequencing

A scheme for vertical migration of algorithms and functions with complex sequencing structure from software through firmware into microcoded VLSI structures is discussed. The expected benefits of migration are gains in speed, reliability, and stability. The scheme employs a migration model that is based on microcode modularity and is supported by a hardware microcontroller with enhanced sequencing capability. The basic idea is to capture, using effective compilation techniques, the explicit or implicit sequencing structure of a function. Migration is then effected by sequencing calls into a library of microcode modules of a target machine architecture. The modularity of the migration system is well suited for generating VLSI microcode. The experimental results from an environment consisting of several firmware development tools show substantial time performance improvements in comparison to software implementations. Comparisons to traditional migration approaches indicate that the proposed scheme is faster and requires less memory space for the migration of software algorithms into firmware.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Learning probabilistic RAM nets using VLSI structures

Hardware-realizable learning probabilistic RAMs (pRAMs) which implement local reinforcement rules utilizing synaptic rather than threshold noise in the stochastic search procedure are described. The design allows for both global and local rewards and penalties (in this latter case implementing a modified version of backpropagation). The architecture allows for serial updating of the weights of a pRAM net according to a reward/penalty learning rule. It is possible to generate a new set of pRAM outputs at least every 100 mu s, which is faster than the response time of biological neurons. >

Modelling and algorithms for spare allocation in reconfigurable VLSI

One approach to enhancing the yield or reliability of large area VLSI structures has been by means of spare interconnect, logic and computational units. Although extensive literature exists concerning design for inclusion of spares and restructuring mechanisms in memories and processor arrays, little research has been published on general models and algorithms for broad classes of spare allocation and reconfiguration problems. The main contribution of the paper is that a novel bipartite graph theoretic approach to spare allocation is presented for structures with dedicated spares and direct replacement reconfiguration. Spare allocation for classes of reconfigurable structures is shown to be equivalent to either a graph matching or a graph dominating set problem. The complexity of optimal spare allocation for each of the problem classes is described, and reconfiguration algorithms are provided. Several detailed examples are presented, and implementation of the algorithms is discussed.

Short note: VLSI Binary-Residue Converters for Pipelined Processing

Residue Number Systems (RNS) are suited for high-speed applications and VLSI implementations, because of the modular and parallel nature of their arithmetic. In this paper a new solution is provided to the problem of designing VLSI structures for converting integers to and from residue number systems in the area of pipelined applications, with the constraint that the layout width is comparable with the data stream width. The proposed structure is suited for both direct and reverse conversion and has complexity figures better than previously known results, evaluated under several hypotheses on the RNS parameters.

Three‐dimensional simulation of VLSI structures

AbstractRecent VLSI technologies allow for increasingly small and complex devices, this calling for three‐dimensional device simulation. In this paper, a 3D simulator is presented: the most relevant problems in its development were found in geometry management and computational efficiency. The adoption of suitable linear solvers enhances the overall computational performance, wihile the prism‐based discretization scheme greatly simplifies most of the geometry‐related algorithms, as demonstrated by the proposed examples, in which complex EPROM‐cell structures are easily handled.

A new test structure for recombination measurements in thin si layers for VLSI structures

AbstractThe capability of two recently proposed measurements methods to evaluate recombination properties of thin layers is discussed. Both methods make use of a novel test structure which allows one to evaluate a) the lifetime profile along submicron epilayers and b) the recombination velocity set by a generic heavily doped layer. Measurements performed on 1 μm thick epilayers demonstrate that the recombination lifetime in these layers is not correlated with the doping level and it has values lower than those reported in thicker layers. Moreover, experimental data collected n+ layers of different technology suggest a phonon‐assisted lifetime value much lower than that reported in literature for uniformly doped bulk material.

Optimal diagnosis procedures for k-out-of-n structures

Diagnosis strategies are investigated for repairable VLSI and WSI structures based on integrated diagnosis and repair. Knowledge of the repair strategy, the probability of each unit being good, and the expected test time of each unit is used by the diagnosis algorithm to select units for testing. The general problem is described, followed by an examination of a specific case. For k-out-of-n structures, a complete proof is given for the optimal diagnosis procedure of Y. Ben-Dov (1981). A compact representation of the optimal diagnosis procedure is described, which requires O(n/sup 2/) space and can be generated in O(n/sup 2/) time. Simulation results are provided to show the improvement in diagnosis time over online repair and offline repair. >

Holographic photolithography for submicron VLSI structures

A holographic method of photo- lithographically printing the image of a photo-mask into a photoresist is presented. The holographic system has been developed for high resolution VLSI integrated circuit manufacture. Submicron images of various typical IC features have been faithfully recorded. The holographic system has also been integrated into a semi-automatic machine, proving the feasibility of integrating and developing the technology into a commercially viable product.

Analogue MOS current-mode circuits for three-dimensional integrated smart image sensor

An image processing technique using analogue MOS current-mode circuits is presented. This approach is of interest in smart image sensors based on three-dimensional (or multi-layered) VLSI structures. High-performance smart image sensors with high resolution can be realised because the number of transistors required for image processing in each pixel is greatly reduced.

DCT algorithms for VLSI parallel implementations

Two algorithms are presented for computing the discrete cosine transform (DCT) on existing VLSI structures. First, it is shown that the N-point DCT can be implemented on the existing systolic architecture for the N-point discrete Fourier transform (DFT) by introducing some modifications. Second, a new prime factor DCT algorithm is presented for the class of DCTs of length N=N/sub 1/*N/sub 2/, where N/sub 1/ and N/sub 2/ are relatively prime and odd numbers. It is shown that the proposed algorithm can be implemented on the already existing VLSI structures for prime factor DFT. The number of multipliers required is comparable to that required for the other fast DCT algorithms. It is shown that the discrete sine transform (DST) can be computed by the same structure. >

Transient radiation effects on VLSI structures

Abstract This paper present theoretical and experimental investigations on the influence of small geometries on latchup effects related to transient radiation effects. Since diffusion current due to ionizing radiation are proportional the square root of the diffusion constant and this quantity varies very little with doping concentrations considered here, useful expressions for radiation induced diffusion currents in VLSI components can be derived. Furthermore a method is presented by which electrical parameters can be measured in order to theoretically predict threshold values for radiation induced latchup.

Selective Oxidation Using Ultrathin Nitrogen‐Rich Silicon Surface Layers Grown by Rapid Thermal Processing

A method for selective oxidation using ultrathin nitrogen‐rich layers (<20Å) grown by rapid thermal processing is presented. Oxidation inhibition in these layers is shown to be a function of the previous oxide layer thickness and the reaction conditions during the rapid thermal nitridation cycle. The oxide growth inhibition property of these layers is tested for rapid thermal and furnace grown oxides. Since oxide growth inhibition appears to be a strong function of the initial oxide thickness, the rapid thermal nitridation process is more controllable than conventional furnace methods because of the shorter exposure time to oxygen contamination. Characterization of the nitridation reaction, the influence of the initial oxide thickness, and the localized inhibition phenomenon are presented with the aim of making this technique useful for novel VLSI structures.

VLSI structures for track finding

We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This “machine” is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of “patterns”. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out.

On sample topography and its influence on the spatial resolution of Scanning Auger Microscopy

The applicability of Scanning Auger Microscopy to the chemical analysis of the micron sized sidewalls of VLSI structures is discussed. Problems arise from scattered primary electrons which cause a considerable decrease of the spatial resolution in the vicinity of edges and steps. It is shown that by making use of the angular emission characteristics of the Auger electrons the interfering signals from adjacent surfaces can be suppressed and the resolution of the sidewall can be improved by more than one order of magnitude.

Efficient covariance ladder algorithms for finite arithmetic applications

This paper is concerned with the problem of constructing numerically robust covariance ladder estimation algorithms for finite arithmetic applications. Conventional least-squares (LS) ladder algorithms suffer from mixed time and order recursive update equations resulting in a poor numerical accuracy when implemented with finite arithmetic. In this paper, a more ‘direct’ and numerically robust computation approach of the ladder update recursions using the most recently introduced algebraic method of generalized residual energies (GRE's) is presented. The new algorithms separate time and order recursions in two independent subalgorithms with a highly modular structure. Besides the general framework, five algorithms of this type are presented. Based on these algorithms, a VLSI ladder chip-set is proposed. Fixed-point simulations of the new VLSI structures are performed for several types of input data. The experimental analysis shows that the new algorithms are superior over conventional techniques and can operate at a multiplier wordlength as low as 8 bits.

An Array Layout Methodology for VLSI Circuits

A new methodology for the layout design of several classes of useful VLSI structures is proposed. The approach produces a structured layout for commonly found computation structures, using regular elements called layout slices. Algorithms for optimal array realization are described that offer several significant advantages over existing layout schemes. Any network that can be decomposed into instances of these structures can therefore be realized using layout slices. Algorithms for the array realization of a class of arbitrary networks are also described. Several well-known structures such as trees, carry-save adders and cube-connected cycles can be realized using the proposed array layout methodology, not only with optimal area but also with several features necessary for practical implementation, e.g., access to key nodes, high area utilization and global signal routing. The proposed methodology is illustrated with actual layouts of useful circuits.

Lower bounds for VLSI implementation of residue number system architectures

Since the number of components that can fit on a single chip is large and rapidly growing, the asymptotic analysis and computational complexity have become applicable to the VLSI systems. We propose a model of computation devoted to VLSI structures based on Residue Number System (RNS). The developed model employs the ‘cut theorem’ which has been used by most of the abstract VLSI models. It is not as general as other reported models, but it gives tighter lower bounds and more accurate measures of performance for RNS structures. This computational model relates the area and time complexities with the inherent properties of RNS, the moduli size and the dynamic range. The model supports the look-up table implementation approach and it is technology-independent.

A technique for modelling p- n junction depletion capacitance of multiple doping regions in integrated circuits

The continuing advancements in integrated circuit technology have placed new burdons on the circuit design engineer, who must rely extensively upon computer simulation to correctly predict circuit behavior. One challenge is to develop better modelling techniques to more accurately deal with complex p- n junction structures often used in modern VLSI designs. This paper presents an easily implemented method for deriving parameters which accurately model the behavior of MOS VLSI structures containing complex p- n junction capacitance components. The methodology is applicable to both planar and laterally diffused junctions, whether formed by direct ion implantation or by diffusion from a finite or infinite source. The theories behind the equations used and results of the application of this new technique are discussed. A flow chart for a fitter program based on the new method is presented and described. The corresponding program written for the TI-59 scientific programmable calculator is available. Final model parameters are given and are shown to produce a numerical capacitance model which is accurate to within 2%.

VLSI Structures for Viterbi Receivers: Part II--Encoded MSK Modulation

As a specific application of the material presented in Part I, this companion paper identifies VLSI layout strategies for realizing correlative encoded MSK-type Viterbi receivers. When the source symbols are correlatively encoded using a first-order polynomial, the appropriate Viterbi receiver takes the form of a cube-connected cycle (CCC) structure. Second-order encoding polynomials give rise to a new type of area-efficient VLSI structure which is a generalization of the CCC structure. The results are important from two perspectives: 1) Isomorphisms between certain concepts in theoretical computer science and digital communications are established, and 2) good practical VLSI layouts are generated, by a structured design methodology, which commercial silicon foundries can fabricate.