Abstract
As a specific application of the material presented in Part I, this companion paper identifies VLSI layout strategies for realizing correlative encoded MSK-type Viterbi receivers. When the source symbols are correlatively encoded using a first-order polynomial, the appropriate Viterbi receiver takes the form of a cube-connected cycle (CCC) structure. Second-order encoding polynomials give rise to a new type of area-efficient VLSI structure which is a generalization of the CCC structure. The results are important from two perspectives: 1) Isomorphisms between certain concepts in theoretical computer science and digital communications are established, and 2) good practical VLSI layouts are generated, by a structured design methodology, which commercial silicon foundries can fabricate.
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