An Array Layout Methodology for VLSI Circuits

Abstract

A new methodology for the layout design of several classes of useful VLSI structures is proposed. The approach produces a structured layout for commonly found computation structures, using regular elements called layout slices. Algorithms for optimal array realization are described that offer several significant advantages over existing layout schemes. Any network that can be decomposed into instances of these structures can therefore be realized using layout slices. Algorithms for the array realization of a class of arbitrary networks are also described. Several well-known structures such as trees, carry-save adders and cube-connected cycles can be realized using the proposed array layout methodology, not only with optimal area but also with several features necessary for practical implementation, e.g., access to key nodes, high area utilization and global signal routing. The proposed methodology is illustrated with actual layouts of useful circuits.