Virtex-5 Field Programmable Gate Array Research Articles

Efficient Implementation of Lightweight MDS Matrix on FPGA

Recently, studying of Maximum Distance Separable (MDS) matrix has become a topic of interest. The MDS matrix is the most important component of the diffusion layer in block ciphers. This paper introduces an optimized, low-cost hardware construction of Galois Field GF(2^8 ) 4×4 MDS matrix. The proposed design is implemented on Field programmable Gate Array (FPGA). The proposed design is synthesized targeting Virtex-7 FPGA using Xilinx ISE Design suite. Xilinx primitives LUT6 and LUT6_2 were used to control exactly the component placement in the design to maintain the minimum occupation area. The pipeline and parallel implementation techniques were used to improve the speed performance. The verification of the functionality of the proposed design has been proved using the ModelSim simulation tool. The synthesis result of the proposed design shows that, the new proposed architecture provides very competitive area and throughput trade-offs. In comparison with other related designs, the proposed design occupies the least area with the minimum time delay. The area of the developed MDS matrix design was significantly reduced, 68 LUT, with high throughput of 21.178 Gbps. The proposed design is a suitable candidate for lightweight cryptographic implementations.

Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory

Field-programmable gate array (FPGA)-based ternary content-addressable memories (TCAMs) are constantly evolving in terms of hardware, power consumption, and speed. One disadvantage of these emulated TCAMs is its poor update-latency. Traditional FPGA-based TCAMs have an update-latency of N clock cycles compared to the lookup-latency of one clock cycle, where N is the depth of TCAM. Later, the update-latency is improved to t clock cycles, where t is the number of don't care bits. In this letter, we presented two mechanisms for updating FPGA-based TCAM and successfully implemented on Xilinx Virtex-6 FPGA: an accelerated MUX-Update mechanism and a cost-effective LUT-Update mechanism. MUX-Update provides an update-latency of W+1 clock cycles by using only three input/output (I/O) pins, whereas W is the width of TCAM. LUT-Update yields a constant update-latency of 2 clock cycles, independent of the size of TCAM, by using W I/O pins.

High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems.

Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.

Smart grid and nuclear power plant security by integrating cryptographic hardware chip

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

A Low-Complexity Edward-Curve Point Multiplication Architecture

The Binary Edwards Curves (BEC) are becoming more and more important, as compared to other forms of elliptic curves, thanks to their faster operations and resistance against side channel attacks. This work provides a low-complexity architecture for point multiplication computations using BEC over GF(2233). There are three major contributions in this article. The first contribution is the reduction of instruction-level complexity for unified point addition and point doubling laws by eliminating multiple operations in a single instruction format. The second contribution is the optimization of hardware resources by minimizing the number of required storage elements. Finally, the third contribution is to reduce the number of required clock cycles by incorporating a 32-bit finite field digit-parallel multiplier in the datapath. As a result, the achieved throughput over area ratio over GF(2233) on Virtex-4, Virtex-5, Virtex-6 and Virtex-7 Xilinx FPGA (Field Programmable Gate Array) devices are 2.29, 19.49, 21.5 and 20.82, respectively. Furthermore, on the Virtex-7 device, the required computation time for one point multiplication operation is 18 µs, while the power consumption is 266 mW. This reveals that the proposed architecture is best suited for those applications where the optimization of both area and throughput parameters are required at the same time.

ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture

In this article, we propose a novel data detection algorithm and a corresponding VLSI design for massive multiuser (MU) multiple-input-multiple-output (MIMO) wireless systems. Our algorithm uses alternating direction method of multipliers (ADMM)-based infinity-norm-constrained equalization and is called ADMIN. ADMIN is an iterative algorithm that outperforms linear detectors by a large margin when the ratio between the numbers of base-station (BS) and user antennas is small. In the first iteration, ADMIN computes the linear minimum mean-square error (MMSE) solution, which is sufficient when the ratio between the numbers of BS and user antennas is large. We develop time-shared and iterative VLSI architectures for LDL-decomposition-based soft-output ADMIN supporting 16- and 32-user systems. We present application-specific integrated circuit (ASIC) designs for 16-64 antenna base stations in 28-nm CMOS that supports up to 64 quadrature amplitude modulation (QAM). The 16-user ADMIN ASIC achieves 303 Mb/s while dissipating 85 mW. The 32-user ADMIN ASIC achieves 287 and 241 Mb/s while dissipating 121 and 135 mW for 32 and 64 BS antennas, respectively. ADMIN has also been implemented on a Xilinx Virtex-7 field-programmable gate array (FPGA) and is compared with state-of-the-art massive MIMO data detectors.

FPGA implementation of digital 3-D image skeletonization algorithm for shape matching applications

ABSTRACT Image skeletonisation plays an important role in applications such as object identification, object’s shape description, pattern recognition, computer vision, telemedicine, and image compression. In this paper, an architecture is developed for the extraction of a skeleton for the 3-D greyscale object. The algorithm used in this paper is an extension of the 2-D greyscale skeletonisation algorithm presented in the literature. The skeleton of a 3-D greyscale object is extracted by using the boundary peeling off method. The skeletonisation algorithms are computationally intensive and difficult to achieve requirements in real-time. Field Programmable Gate Arrays (FPGAs) are selected for implementation so the real-time requirements are met. The proposed architecture is implemented on Virtex-5 FPGA and tested for an 8 × 8 x 3 greyscale object. Resource utilisation of FPGA and timing performance are investigated and are encouraging.

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

This study presents a novel Dormand-Prince-based hybrid chaotic True Random Number Generator Design (TRNG) that can be used for secure communication and cryptographic applications on Field Programmable Gate Array (FPGA). In this design, a chaotic oscillator unit has been implemented with an FPGA-based Sprott-Jafari chaotic oscillator model suitable with IQ-Math fixed point number and IEEE 754-1985 floating point number standards. Random numbers have been produced with the quantization of the results generated by the chaotic oscillator. XOR has been performed with FPGA-based ring oscillator structure on the post-processing unit so as to enhance the randomness. The differential equation of the chaotic system used in the TRNG design was modelled using Dormand-Prince numerical algorithm method. The design on FPGA has been realized in two separate number formats including 32-bit (16I-16Q) IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard. The realized designs have been coded in VHDL, a hardware description language, and the Xilinx ISE 14.7 program has been used for the system design. Two separate TRNG designs have been synthesized and tested for the Virtex-6 (XC6VLX240T-1FF1156) FPGA chip. The maximum operating frequency of the TRNG with 32-bit IQ-Math fixed point number standard is 344.585 MHz and the throughput is approximately 344 Mbit/s. The maximum operating frequency of the TRNG with 32-bit IEEE 754-1985 floating point number standard is 316.756 MHz and the throughput is 316 Mbit/s. 1 Mbit sequence has been generated by both designed TRNG systems. Randomness analysis of the generated numbers has been performed in accordance with the NIST 800-22 tests and the generated numbers have successfully passed all of the tests.

High performance IIR filter implementation on FPGA

This paper presents an improved design of reconfigurable infinite impulse response (IIR) filter that can be widely used in real-time applications. The proposed IIR design is realized by parallel–pipeline-based finite impulse response (FIR) filter. The FIR filters have excellent characteristics such as high stability, linear phase response and fewer finite precision errors. Hence, FIR-based IIR design is more attractive and selective in signal processing. In addition, the other two modern techniques such as look-ahead and two-level pipeline IIR filter designs are also discussed. All the said designs have been described in hardware description language and tested on Xilinx Virtex-5 field programmable gate array board. The implementation results show that the proposed FIR-based IIR design yields better performance in terms of hardware utilization, higher operating speed and lower power consumption compared to conventional IIR filter.

A hybrid hardware oriented motion estimation algorithm for HEVC/H.265

High Efficiency Video Coding (HEVC) is the latest video coding standard that supports high resolution videos by providing approximately twice the compression efficiency as compared to its previous standard H.264. Motion Estimation (ME) in HEVC is the most computation-intensive block as a result it becomes a bottleneck in the design of the encoder while implementing video applications on various computing platforms such as general purpose and embedded processors. So developing computational efficient architectures on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms is inevitable. This paper proposes a fast hybrid search pattern algorithm and its hardware architecture for encoding UHD videos. The proposed Integer ME (IME) algorithm requires an average of 11.19% less encoding time than the default Test Zone Search (TZS) algorithm in HM reference software with compromising decrement in PSNR and increment in bit rate. The proposed architecture is implemented in both FPGA and ASIC platform with TSMC 90 nm technology library. It consumed 32-33% of resources in Virtex-7 FPGA and 2784.4 K equivalent gate count (in terms of NAND ) and 18 kB of memory, respectively. The results show that maximum frequency of the proposed architecture is 162 MHz and a total power consumption is 463.4 mW. The architecture provides a maximum throughput of 2.78 Gpixels/sec due to it process $$32\times 32$$ CU comparatively much less clock cycles (59.5) as compared to the state-of-the-art literature . Further, it supports 8K UHD $$(8192\times 4320)$$ @ 78 fps.

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce’s demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2571) and GF(2283) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2571), which achieves one PM operation in $17.44~\mu s$ using 81549 LUTs (Look-Up-Table) with the frequency of 197.2 MHz on Virtex-5, and $12.55~\mu s$ using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2283) with the shortest computation time. It takes only $3.21~\mu s$ to finish one PM operation on Virtex-5 and $2.22~\mu s$ on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.

FPGA-Based Wigner–Hough Transform System for Detection and Parameter Extraction of LPI Radar LFMCW Signals

Low probability of intercept (LPI) radars using linear frequency-modulated continuous waveforms (LFMCWs) is rapidly proliferating in the military domain and posing a serious challenge to conventional electronic support receivers (ESRs). In this article, we provide a practical approach that can be used in digital ESR systems for real-time LFMCW radar signal detection and parameter extraction under challenging SNR levels. We proposed a modified version of the Wigner–Ville distribution (WVD), namely, short-time Wigner distribution (STWD), postprocessing steps, e.g., column-based thresholding of STWD combined with the Hough transform (HT), and a field-programmable gate array (FPGA) design as an embedded solution with low computational complexity. The performance of the proposed system is tested with MATLAB and hardware simulations using a signal database generated with different signal-to-noise ratio (SNR) levels. The system is then embedded into a Virtex-7 FPGA where the performance evaluations showed satisfactory detection results down to −6-dB SNR level, and parameter extraction results down to −8-dB SNR level.

A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs

Exhaustive verification techniques do not scale with the complexity of today’s multi-tile Multi-processor Systems-on-chip (MPSoCs). Hence, runtime verification (RV) has emerged as a complementary method, which verifies the correct behavior of applications executed on the MPSoC during runtime. In this article, we propose a decentralized monitoring architecture for large-scale multi-tile MPSoCs. In order to minimize performance and power overhead for RV, we propose a lightweight and non-intrusive hardware solution. It features a new specialized tracing interconnect that distributes and sorts detected events according to their timestamps. Each tile monitor has a consistent view on a globally sorted trace of events on which the behavior of the target application can be verified using logical and timing requirements. Furthermore, we propose an integer linear programming-based algorithm for the assignment of requirements to monitors to exploit the local resources best. The monitoring architecture is demonstrated for a four-tiled MPSoC with 20 cores implemented on a Virtex-7 field-programmable gate array (FPGA).

Design and Implementation of Enhanced PUF Architecture onFPGA

ABSTRACT Physical un-clonable functions (PUF) play important role in hardware security due to its random response generation. It offers a wide range of security applications, such as key generation, digital rights management, and Field Programmable Gate Array (FPGA) intellectual property (IP) protection. In literature, several PUF structures of both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) are used to improve the performance parameter, mainly reliability and uniqueness. Because of the large number of challenges and responses pairs (CRPS), Arbiter PUF (APUF) is widely used but suffers from less reliability and uniqueness. The proposed PUF structure is designed to achieve the ideal value of performance metrics and also to reduce the prediction rate. This paper presents a new approach to design Double Feed-Forward XOR Arbiter PUF (DFFX APUF), is a combination of Feed-Forward Arbiter PUF, the output of this combination is XORed to generate the single response. Newly proposed PUF is implemented on Xilinx Virtex-6 FPGA. The reliability and uniqueness are the parameters to evaluate the performance of the DFFX APUF and is compared with the Feed-Froward APUF and Double-APUF. The proposed PUF architecture results, the uniqueness of 5% and reliability of 8% greater than FF-APUF and Double-APUF.

ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah

The advancement of next-generation systems has led to a rapid increase in day-to-day applications by connecting billions of devices. Mobile networks require a considerable cost to support these billions of devices, and conventional IEEE 802.11 is meant for the usage of small-scale applications. To support long-range applications, IEEE task group-ah has proposed a new standard named IEEE 802.11ah. However, it has challenges like efficient device grouping based on variable sampling rates and power consumption. This standard employs orthogonal frequency-division multiplexing as a multicarrier scheme that suffers from high peak-to-average power ratio (PAPR). Hence, to support multiple devices of variable rates in the physical layer along with low PAPR and acceptable bit error rate, a new framework and an optimized architecture of carrier interferometry-group orthogonal–orthogonal frequency-division multiple access architecture is proposed. The proposed architecture reduces the 16-point inverse fast Fourier transform area by 57.1%, device padding area by 50% along with three extra adders functional area compared with the existing architecture. Furthermore, the proposed architecture is prototyped on Virtex5 field-programmable gate array for on-chip validation, and the hardware parameters are measured in real time. The area-timing complexity of the proposed architecture is estimated and further achieves the lowest area- and power-delay product than the existing architecture. Application-specific integrated circuit implementation is carried out using commercially available 32 - nm technology library, where the postlayout results reported less area utilization and low power consumption.

FPGA implementation of an enhanced chaotic-KASUMI block cipher

The radio link is a broadcast channel used to transmit data over mobile networks. Because of the sensitivity of this network part, a security mechanism is used to ensure users’ information. For example, the third generation of mobile network security is based on the KASUMI block cipher, which is standardized by the Third Generation Partnership Project (3GPP). This work proposes an optimized and enhanced implementation of the KASUMI block cipher based on a chaotic generator. The purpose is to develop an efficient ciphering algorithm with better performance and good security robustness while preserving the standardization. The proposed design was implemented on several Xilinx Virtex Field Programmable Gate Arrays (FPGA) technologies. The synthesis results and a comparison with previous works prove the performance improvement of the proposed cipher block in terms of throughput, used hardware logic resources, and resistance against most cryptanalysis attacks.

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.

A Hardware-Efficient and Reconfigurable UFMC Transmitter Architecture With its FPGA Prototype

Universal-filtered multicarrier (UFMC) is one of the potential candidates for 5G multicarrier waveforms due to its several attractive features such as suppressed out-of-band radiation to the nearby sub-band. However, the hardware realization of UFMC systems is limited by a large number of arithmetic units for inverse fast Fourier transform (IFFT) and pulse shaping filters. In this letter, we propose an architecture that presents a refreshing approach toward designing a low-complexity architecture for the baseband UFMC transmitter with Dolph–Chebyshev filter. Compared to the read-only-memory (ROM)-based state-of-the-art, the proposed architecture requires less number of ROM locations and has the flexibility to externally select the inverse discrete Fourier transform (IDFT)-size, number of sub-bands, and number of subcarriers in a sub-band. Moreover, we implement the proposed architecture on a commercially available Virtex-5 field-programmable gate array (FPGA) device for testing and analyzing the baseband UFMC signal. Finally, the XILINX post-route results are found comparable with MATLAB simulations.

HopliteRT: Real-Time NoC for FPGA

With the increasing number of computation nodes integrated in multi and many-core platforms, network-on-chips (NoCs) emerged as a new communication medium in systems-on-chips (SoCs). HopliteRT is a new NoC design that was recently proposed to address the needs of real-time systems whilst respecting the constraints of field-programmable gate array (FPGA) platforms. In this article, we: 1) introduce priority-based routing in HopliteRT; 2) change the network topology in order to improve the packets' worst-case traversal time (WCTT); 3) identify a flaw in the existing timing analysis of HopliteRT; and 4) develop a new timing analysis that is proven correct. We also show by means of experiments that the modifications of HopliteRT proposed in this article allows for at least 2× improvement on the worst and average case traversal time of high priority packets, without impacting the quality of service of low-priority packets. The timing properties of high priority flows are greatly improved for negligible additional hardware costs. The proposed NoC has been implemented in Verilog and synthesized for a Xilinx Virtex-7 FPGA platform.

A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.