A Hardware-Efficient and Reconfigurable UFMC Transmitter Architecture With its FPGA Prototype

Abstract

Universal-filtered multicarrier (UFMC) is one of the potential candidates for 5G multicarrier waveforms due to its several attractive features such as suppressed out-of-band radiation to the nearby sub-band. However, the hardware realization of UFMC systems is limited by a large number of arithmetic units for inverse fast Fourier transform (IFFT) and pulse shaping filters. In this letter, we propose an architecture that presents a refreshing approach toward designing a low-complexity architecture for the baseband UFMC transmitter with Dolph–Chebyshev filter. Compared to the read-only-memory (ROM)-based state-of-the-art, the proposed architecture requires less number of ROM locations and has the flexibility to externally select the inverse discrete Fourier transform (IDFT)-size, number of sub-bands, and number of subcarriers in a sub-band. Moreover, we implement the proposed architecture on a commercially available Virtex-5 field-programmable gate array (FPGA) device for testing and analyzing the baseband UFMC signal. Finally, the XILINX post-route results are found comparable with MATLAB simulations.