ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah

Abstract

The advancement of next-generation systems has led to a rapid increase in day-to-day applications by connecting billions of devices. Mobile networks require a considerable cost to support these billions of devices, and conventional IEEE 802.11 is meant for the usage of small-scale applications. To support long-range applications, IEEE task group-ah has proposed a new standard named IEEE 802.11ah. However, it has challenges like efficient device grouping based on variable sampling rates and power consumption. This standard employs orthogonal frequency-division multiplexing as a multicarrier scheme that suffers from high peak-to-average power ratio (PAPR). Hence, to support multiple devices of variable rates in the physical layer along with low PAPR and acceptable bit error rate, a new framework and an optimized architecture of carrier interferometry-group orthogonal–orthogonal frequency-division multiple access architecture is proposed. The proposed architecture reduces the 16-point inverse fast Fourier transform area by 57.1%, device padding area by 50% along with three extra adders functional area compared with the existing architecture. Furthermore, the proposed architecture is prototyped on Virtex5 field-programmable gate array for on-chip validation, and the hardware parameters are measured in real time. The area-timing complexity of the proposed architecture is estimated and further achieves the lowest area- and power-delay product than the existing architecture. Application-specific integrated circuit implementation is carried out using commercially available 32 - nm technology library, where the postlayout results reported less area utilization and low power consumption.