Very Large Scale Integrated Circuits Research Articles

High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop

With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

TDCM: An IP watermarking algorithm based on two dimensional chaotic mapping

With the rapid development of VLSI (Very Large Scale Integration) circuit, IP (Intellectual Property) protection for reused technology is widely concerned. A watermarking scheme for IP protection is proposed on basis of a two dimensional chaotic mapping model (TDCM). The scheme utilizes a secure and controllable embedding model to compute the aggregation level of physical resource positions and the secure threshold of controllability. A two dimensional chaotic sequence is generated with the control of secure threshold. The first dimensional sequence is used to determine random watermark positions and the second dimensional sequence is to control watermark number in each position. Finally, the watermarks are inserted into corresponding places orderly. The experiments show that the proposed scheme has low resource overhead by comparing with other schemes. The resistance to attacks and robustness of the watermark are encouraging as well.

Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin–Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives

In Part II of this paper, the potential of tunnel FETs (TFETs) for ultra-low voltage (ULV)/ultra-low power (ULP) operation at 32-nm node is investigated through Verilog-A simulations of appropriate reference circuits. Critical issues arising at ultra-low voltages are analyzed, including static robustness of TFET logic gates, performance degradation, and sensitivity to process variations. Guidelines to design ultra-low energy standard cell libraries are derived. The minimum energy point is analyzed in a wide range of conditions, and guidelines for microarchitectural optimization for ultra-low energy are introduced. Voltage scalability of static RAM memories is also analyzed as main limitation to aggressive voltage scaling of very large scale integration (VLSI) systems, and improved precharge schemes are introduced to reduce leakage. The impact of variations of the main device parameters on VLSI digital circuits is investigated to identify the most critical variations that need to be controlled at process level. This investigation permits to understand the potential of TFETs and their advantages over traditional devices within a unitary framework that is based on fair design and comparison from device to circuit level, as well as to develop clear design perspectives in the context of ULV/ULP VLSI digital circuits.

English

Very Large Scale Integration (VLSI) has made a dramatic impact on the growth of integrated circuit technology. It has not only reduced the size and the cost but also increased the complexity of the circuits. The positive improvements have resulted in significant performance/cost advantages in VLSI systems. There are, however, potential problems which may retard the effective use and growth of future VLSI technology. Among these is the problem of circuit testing, which becomes increasingly difficult as the scale of integration grows. Because of the high device counts and limited input/output access that characterize VLSI circuits, conventional testing approaches are often ineffective and insufficient for VLSI circuits. .The vital role of primitive polynomials for designing PN sequence generators. The standard LFSR (linear feedback shift register) used for pattern generation may give repetitive patterns. Which are in certain cases is not efficient for complete test coverage. The LFSR based on primitive polynomial generates maximum-length PRPG.Built-in self-test (BIST) is a commonly used design technique that allows a circuit to test itself. BIST has gained popularity as an effective solution over circuit test cost, test quality and test reuse problems. In this paper we are presenting an implementation of a tester using VHDL

Electromagnetic simulation of VLSI circuits by the modified ADI‐FDTD method

ABSTRACTThe alternating direction implicit (ADI) finite‐difference time‐domain (FDTD) method can be used to simulate very large scale integration (VLSI) circuits efficiently as the time step is not restricted by the Courant–Friedrich–Levy stability condition. When the Berenger's split‐field perfectly matched layer (PML) absorbing boundary condition is used for the ADI‐FDTD method for open region simulation, the PML implementation will make this scheme unstable. In this article, the modified PML conductivity profiles are proposed to improve the stability of this scheme. Numerical simulations of the VLSI interconnect and RF inductor in time domain and frequency domain will be demonstrated to show the efficiency and accuracy of this method. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2530–2534, 2014

Space Time Block Code Analysis for MIMO-OFDM System

The growth in high data rate mobile data transmission in recent years is due to the tremendous achievements in Digital Communication especially Digital Modulation Techniques starting from Second Generation system (2G) in early 80’s to today 4G (LTE – Advanced). To achieve the goal towards Shannon’s Channel Capacity, a no. of modulation techniques are developed during these years. With the tremendous growth in the Very Large Scale Integrated Circuits (VLSI), a no. of digital modulation techniques is easier to implement in convenient manner. Orthogonal Frequency Division Multiplexing (OFDM), one of the latest techniques became feasible and economical due to the high processing speed. OFDM in combination with other techniques like Space Time Block Code (STBC)Phase shift key (PSK) and Quadrature Amplitude Modulation (QAM) give better performances in case of Multiinput Multi-output System (MIMO). This paper presents (STBC) technique for multiple transmission antennae (OFDM) system. Generally in Multiinput Multioutput (MIMO) system code selection across the space and time is difficult to get minimum Bit Error (BER) to achieve maximum output. In adaptive White Gaussian (AWGN) fading channels, STBC is best breakthrough to reduce the BER and obtain maximum output. Like AWGN fading channel the analysis is done for OFDM system using STBC at transmitter end. Various modulation techniques like Binary Phase Shift Key (BPSK) and Quadrature Amplitude Modulation are implemented using mentioned techniques. The Bit Error Rate (BER) versus different Signal to Noise (SNR) ratio are studies for above modulation techniques.

Predict VLSI Circuit Reliability Risks Using Neural Network

This paper describes the challenges faced in predicting the reliability of very large scale integration (VLSI) circuits. Currently, lots of trial-and-errors are still needed for the parameters selected to develop a neural network prediction model, whose result is with a great deal of uncertainty. The objective of this paper is to provide a novel and practical approach to design a reliability prediction model using neural network. We propose a seven-step procedure to formulate an optimal neural network design and explain it in details using a case study on semiconductor reliability. We combine reliability test characteristics (e.g., early failures) with statistical methods such as regression and design of experiment (DOE) for this optimal neural network model and get comparably small prediction errors. Following our proposed approach, analysts can develop effective designs with higher prediction accuracy. We further introduce an operation flow to maximize the benefits from the obtained optimal prediction model by earlier nonconformance detection and faster lot dispositions, which are reported in the case study on successfully implementing our methodology to predict inter metal dielectric (IMD) reliability risks. Our proposed approach can be easily applied on many other fields like yield prediction.

Performance and Analysis of Voltage Scaled Repeaters for Multi-Walled Carbon Nanotubes as VLSI Interconnects

Multi-walled carbon nanotubes (MWCNT) are promising candidates for futuristic Nano-electronic applications. MWCNT have potential to replace on-chip copper (Cu) interconnects due to their large conductivity and current carrying capabilities. Delay is one of the major design constraints in very large scale integration (VLSI) circuits. This paper presents an analysis of propagation delay and effect of repeater insertion on propagation delay for both MWCNT and Cu interconnects at different technology nodes viz 32nm and 22nm. In addition this paper deals with effect of voltage scaling in repeaters for long interconnects length in VLSI circuits in terms as propagation delay. It has been observed that propagation delay reduces with increase in bias voltage of the repeater at different interconnects length and technology nodes (32nm.22nm).

EFFICIENT DELAY AND CROSSTALK ESTIMATION MODELS FOR CURRENT-MODE HIGH SPEED INTERCONNECTS UNDER RAMP INPUT

In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring based model with 1% error is in very good agreement with HSPICE for line lengths 0.1–0.5 cm. The estimated crosstalk induced delay values of proposed model maximum error percentage is nearly half of the extended Eudes model. For both single and three coupled interconnect lines, the proposed model is in good agreement with HSPICE.

A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems

With the advanced technology used to design VLSI (Very Large Scale Integration) circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS) and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works.

Emerging Applications for High K Materials in VLSI Technology.

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

POWER EFFICIENT AND HIGH THROUGHPUT OF FIR FILTER USING BLOCK LEAST MEAN SQUARE ALGORITHM IN FPGA

In silicon on chip technology demands high performance and low power Very Large Scale Integrated Circuit (VLSI) digital signal processing (DSP) systems. The aim of this paper explores the power consumption technique for the architecture of Finite Impulse Response (FIR) adaptive filter. An adaptive FIR filter with Block Least Mean Square (BLMS) algorithm was developed to reduce the power. Distributed arithmetic (DA)-based formulation of BLMS algorithm is used to reduce the area where both convolution operation to compute filter output and correlation operation to compute weight-increment term could be performed by using the same LUT. Thus a DA based implementation of adaptive filter is highly computational and area efficient.

A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT

The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are clustered into blocks by recursively partitioning; (2) a floorplanning algorithm is performed on every level of the blocks; (3) the macro cells are shifted by a macro shifting technique to determine their exact locations; (4) with each macro cell location fixed, a standard cell placement algorithm is applied to place the remaining objects. The proposed approach is tested on the IBM mixed-size benchmarks and the modern mixed-size (MMS) placement benchmarks. Experimental results show that our approach outperforms the state-of-the-art placers on the solution quality for most of the benchmarks.

Ion implantation technology and ion sources

Ion implantation (I/I) technology has been developed with a great economic success of industries of VLSI (Very Large-Scale Integrated circuit) devices. Due to its large flexibility and good controllability, the I/I technology has been assuming various challenging requirements of VLSI evolutions, especially in advanced evolutional characteristics of CMOSFET. Here, reviewing the demands of VLSI manufacturing to the I/I technology, required characteristics of ion implanters, and their ion sources are discussed.

스테레오 비전을 위한 고성능 VLSI 구조

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of 640×480.

An Application of Rectilinear Embedding in VLSI Placement

The VLSI (Very Large Scale Integrated Circuits) technology has developed rapidly in recent years, with a lot of advanced electric products emerging. Placement layout is regarded as the initial step in VLSI physical design. Its quality has a direct effect on the chip area and performance. The rectilinear embedding, which originates from graph theory, is widely employed in VLSI placement. In this paper, we set up a mathematical model for VLSI. Firstly, the issue of VLSI placement was converted to quadrangulation by using rectilinear embedding. Then we provided generating functions for two types of quadrangulations with graph multiple parameters. And the explicit formulae by employing Lagrangian inversion were obtained. Furthermore, we found the relation between outerplanar graph and Hamilton graph, so the counting result of Hamilton quadrangulation was derived. The quadrangulation calculation can be applied to the establishment of a computerized algorithm, which can be widely used for VLSI placement optimization.

Design and Implementation of a Joint Data Compression and Digital Watermarking System in an MPEG-2 Video Encoder

With the rapid distribution of digital video capture devices, significant videos can be captured effortlessly. The captured videos are often saved in moving pictures expert group-2 (MPEG-2) format. To prove copyright ownership, applying watermarking in MPEG-2 videos is necessary. However, little research has been devoted to the watermarking design not only for the spatial domain but also for the frequency domain and the realization of watermarking hardware. Thus, a joint data compression and watermarking system with configurable spatial and frequency domain embedding, and its very large scale integrated circuit (VLSI) architecture is presented in this paper. First, after analyzing the characteristics of videos, a novel watermarking system with two number-based keys and a shuffled image is built. It is based on the spread spectrum techniques and adaptive human visual system (AHVS). With a consideration of the cost and easiness of use, the proposed system is realized as blind detection which can dispense without the storage of the original-multimedia data. Second, the efficient VLSI architecture of our approach is designed. Various subjective and objective evaluations are performed for watermarking analysis. From the evaluation, it is realized that the system can achieve robust watermarking with high flexibility for joint data compression and low hardware complexity. Various attacks and comparisons also show the efficiency of the proposed watermarking scheme. Furthermore, the VLSI synthesis results demonstrate the high performance of the proposed architecture. Thus, the proposed system is adequate for a specific function intellectual property (IP) combined with a real-time video capture and a surveillance system.

Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors

With the advancement of fabrication technology, the electrostatic coupling has increasing impact on the performance of very large-scale integrated (VLSI) circuits and micro-electromechanical systems (MEMS). For the structures in VLSI circuits which are mostly rectilinear geometries, the floating random walk (FRW) method using cubic transition domains has been successfully applied to calculate the electric capacitances among interconnect wires. In this work, the techniques of importance sampling and stratified sampling are presented to accelerate the FRW algorithm by improving the convergence rate of the Monte Carlo procedure. An efficient approach is then presented to parallelize the FRW algorithm with the graphic processing units (GPUs). GPU-friendly algorithmic flow and data structure are designed to reduce the divergence among random walks and the time of accessing the device memory. The presented techniques are also applicable to the calculation of electric field intensity, which is also an important problem for nowadays nanometer-technology circuits. Numerical results are presented with several simple structures and larger ones from real VLSI circuits or MEMS. The results validate the accuracy of the presented techniques and demonstrate up to 100× speedup due to the variance reduction and GPU-based parallel computing.

Power Analysis for Deep Submicrometer Conventional MOS Transistors

Power dissipation of very large scale integrated circuits (VLSI) has emerged as a significant constraint on the semiconductor industry. For the dynamic power the voltage, capacitance and frequency are the major components of the power dissipation. In this paper, we propose a new power macromodeling technique for the power estimation of complementary metal-oxide- semiconductor (CMOS) inverter using 0.12μm technology. As the dynamic power is directly linked with the load capacitance (CL), it is also a lumped capacitance of all internal parasitic capacitances. In our model, we take an account of the parasitic capacitances with their dependence on channel width and the length. Suitable values of other factors (i.e. threshold voltage VT, gate voltage VGS, drain voltage VDD etc.) are used for the power consumption of the CMOS inverter. The Preliminary results are effective and our macromodel provides the accurate power estimation.