Very Large Scale Integrated Circuits Research Articles

BSIM3 model parameter extraction and performance analysis of a strained p-MOSFET for digital applications

Strain is one of the conventional methods used to enhance the mobility of carriers in metal–oxide–semiconductor field-effect transistors (MOSFETs). The strain is generated due to the lattice mismatch between the thin Si layer and underlying SiGe layers and reduces the effective mass of holes and inter-subband scattering. A compact model for such devices is essential to promote the design of very large-scale integration (VLSI) circuits using strained p-MOSFETs. In this paper, for the first time we propose to use the BSIM3 model for biaxially strained p-MOSFETs, using a proper parameter extraction method. The extracted model parameters are validated by comparing the results with technology computer-aided design (TCAD) simulations and a simple analytical model. The average error in the direct-current (DC) and alternating-current (AC) characteristics of the model is estimated to be below 1.5%. Finally, the extracted model is used to analyze the performance of several digital gates, including inverter, NAND, NOR, and static random-access memory (SRAM) cells, based on the strained p-MOSFET as a key circuit component. The simulation results show significant performance improvements of the gates in terms of the area, propagation delay, dynamic power consumption, static noise margin, and functional symmetry. By using strained p-MOSFETs in the SRAM cell, the active area of transistors can be reduced by up to 28.8% while at the same the time static power consumption is reduced by 4.8%, the static noise margin is increased by 10.5%, and the write access time is reduced by about 15.6%. These results not only suggest that the strained Si p-MOSFET can improve the performance of VLSI circuits but also confirm that the BSIM3 model with an appropriate parameter extraction method can be used for the design of digital circuits using strained p-MOSFETs.

Analyzing Clustering and Partitioning Problems in Selected VLSI Models

As the modern integrated circuit continues to grow in complexity, the design of very large-scale integrated (VLSI) circuits involves massive teams employing state-of-the-art computer-aided design (CAD) tools. An old yet significant CAD problem for VLSI circuits is physical design automation. In physical design automation, we need to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface. The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for combinatorial circuits, there are several models for the clustering problem. In particular, we consider the problem of clustering without replication in combinatorial circuits with a view towards minimizing delay (CN). The corresponding problem with replication has been well-studied and solvable in polynomial time. However, replication can become expensive when it is unbounded. Consequently, CN is a problem worth investigating. We establish the computational complexities of several variants of CN. Additionally, we obtain approximability and inapproximability results for some NP-hard variants of CN. We also present approximation and exact exponential algorithms for some variants of CN. We prove that for some cases there exists an approximation factor of strictly less than two and that our exact exponential algorithms beat brute force. Furthermore, we provide the first parameterized approximation algorithm in which the approximation ratio is also a parameter.

Crosstalk-Aware Global Routing in VLSI Design by Using a Shuffled Frog-Leaping Algorithm

Nowadays, very large scale integrated (VLSI) circuit technology is developing rapidly. It is necessary to consider many factors related to the VLSI circuit design. Interference is one of the factors that must be considered in high-frequency systems. The parasitic elements become serious limiting factors in the circuit. This research provided a method to reduce crosstalk energy by considering the transition of the signal. Crosstalk is the main capacitive effect which is elected by a high-coupling capacitance between lines. This study considers the wiring path signal with disturbance using the theory of optimization model, assisting in the search of the best sort in signal lines. The technique of a shuffled frog leaping algorithm (SFLA) is being used to search for the best value in arranged signal lines. The result will be minimal noise. The study finds that the arrangement using the SFLA causes only 36.42% of the noise. It was initially evident and 13.06%, when compared with the average all, is born noise value. These techniques can be applied in the design of arranging signal line in the VLSI circuits.

VLSI for Next Generation CE

The current research in VLSI explores emerging trends and novel ideas and concepts covering a broad range of topics in the area of VLSI: from VLSI circuits, systems, and design methods, to system-level design and systemon- chip issues, to bringing VLSI methods to new areas and technologies such as nano and molecular devices, MEMS, and quantum computing. Future design methodologies are also key topics of Very Large Scale Integration (VLSI) research, as well as new Electronic Design Automation (EDA) tools to support them. The purpose of this special section is to provide an insight into current research and development in aspects related to ISVLSI.

Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.

An efficient VLSI circuit partitioning algorithm based on satin bowerbird optimization (SBO)

In partitioning, a circuit is recursively divided into several subcircuits so that each can be efficiently and independently designed with the main objective of reducing the cut-cost. Partitioning is a first step in the very large-scale integration (VLSI) physical design process, and all the other physical design steps such as floorplanning, placement, pin assignment, and routing depend on its outcome. The partitioning determines the overall quality of the final layout, since the use of an incorrect partitioning can degrade the performance of all subsequent phases of the physical design process. A novel partitioning algorithm based on the concept of satin bowerbird optimization (SBO) is proposed herein. The bioinspired SBO algorithm chooses the initial partitions randomly then utilizes the concepts of fitness value evaluation and group migration to improve the cut-cost. The performance of the proposed algorithm is evaluated using parameters such as the cut-cost and time complexity based on simulations with ISCAS’85 benchmark circuits. The performance parameters of the circuits, i.e., area, power, and delay, are evaluated before and after partitioning. The proposed bioinspired SBO algorithm is compared with similar bioinspired algorithms such as ant colony optimization, particle swam optimization, genetic, and firefly algorithms.

A novel implementation of combined systolic and folded architectures for adaptive filters in FPGA

The adaptive filter constitutes an important part of statistical signal processing. Adaptive filters are often realized either as a set of program instructions running on an arithmetical processing device such as a Microprocessor or Digital Signal Processing (DSP) chip, or as a set of logic operations implemented in a field programmable gate array (FPGA) or in Very Large Scale Integrated Circuit (VLSI). Systolic architecture improves the speed of the system at the cost of increased area. On the other hand, folding technique uses less hardware resources. A combination of systolic and folding structures provides improvement in speed and reduction in area. This paper presents a novel idea of combining Systolic and Folding architectures and its design in various adaptive filters like Recursive Least Square (RLS), Affine Projection (AP) and Kalman filters. The structures are designed using Xilinx System Generator tool of MATlab 2015 and implemented in Xilinx Virtex 5 FPGA. The designed structures are tested for noise cancellation in Electrocardiogram (ECG) signal and results are analysed for various order of all the filters and its metrics are analysed in terms of Signal to Noise Ratio(SNR), Mean Square Error(MSE), area and speed. From the analysis it is observed that the proposed folding in systolic structures improves SNR by 6.77% in RLS, 4.68% in Affine projection and 2.13% in Kalman Algorithm than the conventional structures. It is inferred that the proposed design in Affine projection shows improved SNR than the other filters. The proposed combined folding in systolic architecture shows 18.35% reduction in area and reduction in delay.

Impact of Variation of Device Parameters on the Electrical Characteristics of Double-Gate Mosfets

Very large scale integrated circuits (VLSI) have been possible owing to the shrinking of metal-oxide semiconductor field-effect transistors (MOSFETs). By reducing the dimensions of the device it is possible to have high density on the chip. This increases the number of logical functions that can be implemented on a given dimension of the chip. Along with the advantages associated with the shrinking of the devices, it also has certain drawbacks commonly known as short-channel effects. Due to these effects, device characteristics deviate from its expected values. There are many techniques through which these deviations can be minimized. One of the promising and highly researched techniques these days is the use of Multi-gate (MG) transistors in VLSI. Double-gate (DG) transistor is one among MG transistors. In DG MOSFET, substrate is surrounded by gates from two opposite sides. This leads to more control over the channel electrons by the gate terminals. In this paper, the consequence of change of various device constraints on the electrical characteristics of the DG MOSFETs will be investigated. Through the results, one can know to what extent the electrical properties changes when the dimensions and/or material properties are changed. This will be very helpful in determining the maximum current associated with those dimensions of DG MOSFETs.

Designing dual-chirality and multi-Vtrepeaters for performance optimization of 32 nm interconnects

PurposeThis paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vttechnology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm.Design/methodology/approachUsually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vttransistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control.FindingsAn unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes.Originality/valueResult analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

SummaryNetwork‐on‐chip (NoC) is a new design method of system‐on‐chip used in very large scale integrated circuit (VLSI) systems. It is an important issue for choosing the appropriate topology for NoC. Wirelength and layout area are significant parameters affecting NoC due to the restriction of chip area. In this paper, we propose a new interconnection network called the incomplete ternary n‐cube for parallel computing systems. Then, a linear algorithm is proposed to layout incomplete ternary n‐cube network onto torus NoC. Furthermore, the failure of interconnection network is also taken into account, and a fault‐tolerant layout of incomplete ternary n‐cube with faulty edges into torus NoC is verified. Theoretical analysis demonstrates that the proposed algorithm can reduce the network cost and wirelength, which be conducive to estimate the wire length and chip area.

Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization

Energy dissipation is a prominent factor for the very large scale integrated circuit (VLSI). The reversible logic-based circuit was capable to compute the logic without energy dissipation. Accordingly, reversible circuits are an emerging domain of research based on the low value of energy dissipation. At nano-level design, the critical factor in the logic computing paradigm is the fault. The proposed methodology of fault coverage is powerful for testability. In this article, we target three factors such as fault tolerance, fault coverage and fault detection in the reversible KMD Gates. Our analysis provides good evidence that the minimum test vector covers the 100 % fault coverage and 50 % fault tolerance in KMD Gate. Further, we show a comparison between the quantum equivalent and controlled V and V+ gate in all the types of KMD Gates. The proposed methodology mentions that after controlled V and V+ gate based ALU, divider and Vedic multiplier have a significant reduction in quantum cost. The comparative results of designs such as Vedic multiplier, division unit and ALU are obtained and they are analyzed showing significant improvement in quantum cost.

Adaptive wavelet ELM-fuzzy inference system-based soft computing model for power estimation in sustainable CMOS VLSI circuits

Rapid growth of very large-scale integration (VLSI) technologies has achieved integrating millions of transistors into a single chip. This integration into a single chip results in complex circuitry, and hence, it is required to have minimal cost and low complex power estimation approaches. Power estimation of VLSI circuits at an initial stage is most prominent because it increases the life and stability of the circuit. In this work, a modified version of extreme learning machine (ELM) neural network called as adaptive wavelet extreme learning machine neural network model (AWELM) is developed and integrated with a designed fuzzy inference system (FIS) for computing power in respect of standard International Symposium on Circuits and Systems 1989 (ISCAS 1989) benchmark circuits. The proposed method is devised to estimate the power accurately for the complementary metal oxide semiconductor VLSI circuits. The developed method does not require prior knowledge about the circuit architecture and its connections. The new AWELM-FIS technique developed in this paper estimates the power in the circuit based on the input and output information and various data of gates pertaining to VLSI circuit itself. The developed method is investigated for its validity and effectiveness by comparing it with the existing methods reported in earlier literature studies, and to train the new model, the results presented in the literature of ISCAS 1989 have been employed. Results prove the effectiveness of newly proposed AWELM-FIS approach over all other compared methods from the existing literatures.

Wolf pack algorithm for solving VLSI design tasks

The paper deals with the development of new and modified heuristic mechanisms of searching optimal solutions, which is considered as one of the main problems of artificial intelligence. One of the promising areas of artificial intelligence development is application of methods and models of biological systems behavior for solving NP-complete and NP-difficult optimization tasks. The paper presents the statement of the placement task in designing very large-scale integration circuits (VLSI). The authors propose the algorithm for solving this task on the basis of biological system behavior in nature, e.g. wolf pack. Wolves are considered as typical social animals having clear separation of social work. The paper describes the actions and rules of wolf pack behaviour in nature. Based on the wolves’ behaviour rules and actions, the authors present the modified wolf pack algorithm. The benefits of the developed modified algorithm include the ability to improve each following iteration of the placement task. The wolf pack algorithm is implemented as a computer software on Java. To estimate the effectiveness of the proposed approach, the authors use the well-known IBM benchmarks to compare with the developed algorithm. The comparison is implemented with the results of the following algorithms: Capo 8.6, Feng Shui 2.0, Dragon 2.23. The results show that the wolf pack algorithm is more effective than the analogues.

Modeling of Superconducting Passive Transmission Lines

Superconducting technologies are moving toward very large-scale integration (VLSI) of circuits. Passive transmission lines (PTLs) are used to quickly and efficiently propagate single flux quantum pulses between separated logic elements of these VLSI circuits. PTLs are often insufficiently modeled to correspond to reality. Therefore, the PTL needs to be thoroughly studied to determine realistic propagation characteristics. A quasi-transverse magnetic (TM) formulation is used to study superconducting passive transmission lines. The ambient temperature and changes in penetration depth with frequency are taken into account when solving the electromagnetic fields of a PTL. Per-frequency transmission line parameters are extracted from the quasi-TM field solutions. The results show a very close correlation to TetraHenry, an existing 3D solver, at significantly reduced computational cost. The results also clearly show that PTL propagation characteristics are sensitive to frequency and temperature.

Analysis of Clock Single-Event Transients in VLSI Through Built-In Scan Chains

The single-event transients (SETs) have become a main contributor to soft errors in deep sub-micrometer integrated circuits applied in space. The sensitivity of 65-nm very large scale integrated circuits (VLSI) to SET, especially to clock SET, is studied by heavy ion experiments and analyzed. Built-in scan chains in the VLSI are utilized for experimental tests and proven to be very useful for SET evaluation. The specially designed test chip is developed and tested to find the relation between errors’ distribution and clock tree structures. Error count per event (EPE) is proposed as a metric of SET, and EPE distribution is found to be able to reflect error sources in the circuit topology. The related mechanisms are analyzed and implications for error positioning and design enhancement are given.

Analysis and minimization of crosstalk noise in copper interconnects for high-speed VLSI circuits

Due to the rapid advances of technologies, the scaling of parameters are decreasing. In VLSI (Very Large Scale Integration) technology, the feature size of integrated circuits (IC) has driving reduced in terms of power, speed, area and cost characteristics. The decreasing the sizes in sub-quarter microns, spacing between the components on-chip VLSI design and the signal switching time in terms of pico seconds or even less. As a result, the signal integrity (SI) issues are occurring at higher frequencies and high data rates. The evaluation of crosstalk noise between the coupled interconnect is one of the prominent issue in designing of high-speed ICs. In this paper, investigated the crosstalk noise of coupled copper (Cu) interconnect models with analytically at 32 nm technology nodes. Also, investigated the crosstalk reduction with shield insertion technique and increasing physical spacing between the coupled lines. For the low power VLSI applications, the shield insertion technique is preferable for reducing the crosstalk effects in coupled interconnects.

Sub-terahertz testing of millimeter wave Monolithic and very large scale integrated circuits

Comprehensive Testing of Microwave Monolithic Integrated Circuits (MMICs) and Very Large Scale Integrated (VLSI) circuits is a problem of growing sophistication and importance. A commensurate problem involves the increasing relevance of hardware security, with rapidly increasing dependence of U.S. industry on imported electronics. Non-destructive, unobtrusive testing techniques are especially useful but hard to implement. In this paper, we report on using THz scanning of MMICs and VLSI circuits for testing, identification, and validation by measuring the circuit response at the pins. This technique could also be used to evaluate the reliability and lifetime of integrated circuits. This technique was demonstrated using a working and damaged MMIC with just a few transistors. For larger-scale circuits, this technique can be combined with machine learning for establishing the evolving database of the responses processed by an artificial-intelligence algorithm.

Clustering without replication in combinatorial circuits

The modern integrated circuit is one of the most complex products engineered to date. It continues to grow in complexity as years progress. As a result, very large-scale integrated (VLSI) circuit design now involves massive design teams employing state-of-the-art computer-aided design (CAD) tools. One of the oldest, yet most important CAD problems for VLSI circuits is physical design automation, where one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface (Lim in Practical problems in VLSI physical design automation, Springer, Dordrecht, 2008). The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for combinatorial circuits, there exists several models for the clustering problem. In particular, we consider the problem of clustering in combinatorial circuits for delay minimization, without permitting logic replication (CN). The problem of clustering for delay minimization when logic replication is allowed (CA) has been well-studied and is known to be solvable in polynomial time (Lawler et al. in IEEE Trans Comput 18(1):47–57, 1969; Rajaraman and Wong, in: 30th ACM/IEEE design automation conference, pp 309–314, 1993). However, unbounded logic replication can be quite expensive. It follows that CN is an important problem. We show that selected variants of CN are NP-hard. We also obtain approximability and inapproximability results for some of these problems. A preliminary version of this paper appears in Donovan et al. (in: 9th International conference on combinatorial optimization and applications, COCOA 2015, Proceedings, pp 334–347, 2015).

30-nm Contacted Gate Pitch Back-Gate Carbon Nanotube FETs for Sub-3-nm Nodes

Carbon nanotube FETs (CNFETs) promise significant energy efficiency benefits versus silicon for digital systems. While these projected benefits are for CNFETs with similar geometries as silicon FETs (e.g., top-gate FETs, with the FET gate on top of the channel), the majority of the demonstrated CNFETs leverage back-gate geometries due to ease of fabrication (i.e., the gate is fabricated before and underneath the FET channel). Although back-gate CNFETs have already been experimentally demonstrated, importantly, there lacks any rigorous analysis of their benefits for digital very-large-scale integrated (VLSI) circuits. Here, we rigorously quantify, for the first time, the benefits of back-gate geometries: both for enabling aggressive device scaling as well as VLSI circuit energy-delay product (EDP) benefits. The key contributions of this paper are: 1) first analysis of back-gate FET geometries for digital VLSI circuits, showing they enable >1.6× additional EDP benefit for CNFETs due to reduced parasitic capacitances (versus top-gate CNFETs), 2) our analysis shows that leveraging back-gate FETs enables aggressive FET scaling to sub-3-nm technology nodes, and 3) as a feasibility case study, we experimentally realize digital logic circuits that fit within the world's smallest contacted gate pitch to date (CGP, a key metric defining the area of an FET and consequently the technology node) of 30 nm.

Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

The interconnect temperature of very large scale integration (VLSI) circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.