Analysis of Clock Single-Event Transients in VLSI Through Built-In Scan Chains

Abstract

The single-event transients (SETs) have become a main contributor to soft errors in deep sub-micrometer integrated circuits applied in space. The sensitivity of 65-nm very large scale integrated circuits (VLSI) to SET, especially to clock SET, is studied by heavy ion experiments and analyzed. Built-in scan chains in the VLSI are utilized for experimental tests and proven to be very useful for SET evaluation. The specially designed test chip is developed and tested to find the relation between errors’ distribution and clock tree structures. Error count per event (EPE) is proposed as a metric of SET, and EPE distribution is found to be able to reflect error sources in the circuit topology. The related mechanisms are analyzed and implications for error positioning and design enhancement are given.