Very Large Scale Integrated Circuits Research Articles

An Efficient On-Chip Data Storage and Exchange Engine for Spaceborne SAR System

Advancements in remote sensing technology and very-large-scale integrated circuit (VLSI) have significantly augmented the real-time processing capabilities of spaceborne synthetic aperture radar (SAR), thereby enhancing terrestrial observational capacities. However, the inefficiency of voluminous data storage and transfer inherent in conventional methods has emerged as a technical hindrance, curtailing real-time processing within SAR imaging systems. To address the constraints of a limited storage bandwidth and inefficient data transfer, this study introduces a three-dimensional cross-mapping approach premised on the equal subdivision of sub-matrices utilizing dual-channel DDR3. This method considerably augments storage access bandwidth and achieves equilibrium in two-dimensional data access. Concurrently, an on-chip data transfer approach predicated on a superscalar pipeline buffer is proposed, mitigating pipeline resource wastage, augmenting spatial parallelism, and enhancing data transfer efficiency. Building upon these concepts, a hardware architecture is designed for the efficient storage and transfer of SAR imaging system data, based on the superscalar pipeline. Ultimately, a data storage and transfer engine featuring register addressing access, configurable granularity, and state monitoring functionalities is realized. A comprehensive imaging processing experiment is conducted via a “CPU + FPGA” heterogeneous SAR imaging system. The empirical results reveal that the storage access bandwidth of the proposed superscalar pipeline-based SAR imaging system’s data efficient storage and transfer engine can attain up to 16.6 GB/s in the range direction and 20.0 GB/s in the azimuth direction. These findings underscore that the storage exchange engine boasts superior storage access bandwidth and heightened data storage transfer efficiency. This considerable enhancement in the processing performance of the entire “CPU + FPGA” heterogeneous SAR imaging system renders it suitable for application within spaceborne SAR real-time processing systems.

Verification methods for complex-functional blocks in CAD for chips deep submicron design standards

The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.

Intelligent Systems and Photovoltaic Cells Empowered Topologically by Sudoku Networks

A graph invariant is a number that can be easily and uniquely calculated through a graph. Recently, part of mathematical graph invariants has been portrayed and utilized for relationship examination. Nevertheless, no reliable appraisal has been embraced to pick, how much these invariants are associated with a network graph in interconnection networks of various fields of computer science, physics, and chemistry. In this paper, the study talks about sudoku networks will be networks of fractal nature having some applications in computer science like sudoku puzzle game, intelligent systems, Local area network (LAN) development and parallel processors interconnections, music composition creation, physics like power generation interconnections, Photovoltaic (PV) cells and chemistry, synthesis of chemical compounds. These networks are generally utilized in disorder, fractals, recursive groupings, and complex frameworks. Our outcomes are the normal speculations of currently accessible outcomes for specific classes of such kinds of networks of two unmistakable sorts with two invariants K-banhatti sombor (KBSO) invariants, Irregularity sombor (ISO) index, Contraharmonic-quadratic invariants (CQIs) and dharwad invariants with their reduced forms. The study solved the Sudoku network used in mentioned systems to improve the performance and find irregularities present in them. The calculated outcomes can be utilized for the modeling, scalability, introduction of new architectures of sudoku puzzle games, intelligent systems, PV cells, interconnection networks, chemical compounds, and extremely huge scope in very large-scale integrated circuits (VLSI) of processors.

A Review on low-Power VLSI CMOS and CNTFET Circuits

Nowadays, power consumption is one of the primary considerations in the design of VLSI (Very Large Scale Integration) circuits based on complementary metal oxide semiconductors (CMOS) and carbon nanotube field effect transistors (CNTFET). This is because of the present circumstance. The fundamental reason for this is that power utilisation has been raised to the status of a top priority due to the improvements in integration and scaling as well as the constant increases in operating frequency. Additional power consumption from circuits and designs makes them challenging to implement in portable devices. The quantity of power lost during operation has an immediate effect on the cost of packaging the IC and systems. A variety of power dissipation sources and low power VLSI design strategies for CMOS and CNTFET-based circuits are discussed in this article.

Research Progresses on Suppressing the Short-Channel Effects of Field-Effect Transistor

Recently, with the continuous miniaturization and integration of microelectronic devices in all fields, the conventional MOSFET structure has suffered from severe short channel effects with continuous downsizing. In order to further improve the electrical properties of Very Large-Scale Integration Circuit (VLSI) and obtain the larger device integration density in circuits, new revolution in MOSFET technology is needed, which involves the innovations of new materials, new technologies, and new device structures. This paper explores device structure innovations in traditional planar transistors, such as the device performance enhancement via the high-κ/metal gate and especially the three-dimensional device structure—FinFET, as well as the subsequent development of gate-all-around FET proved to outperform FinFET. The development of high-performance devices based on new materials has become an imperative direction to break through the current bottleneck of silicon-based technologies. This paper focuses on an overview of transition-mental dichalcogenides and ferroelectric materials, including frontier research and current inadequacies. Based on these new approaches, VLSI manufacturing technology has seen many breakthroughs in recent years, which will successfully extend Moore's Law and further promote the development of emerging technologies in multiple fields.

A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing

The electromigration (EM)-induced reliability issues in very large-scale integration (VLSI) circuits have attracted increased attention due to the continuous technology scaling. Traditional EM models often lead to overly pessimistic predictions incompatible with the shrinking design margin in future technology nodes. Motivated by the latest success of neural networks in solving differential equations in physical problems, we propose a novel mesh-free model to compute EM-induced stress evolution in VLSI circuits. The model utilizes a specifically crafted space–time physics-informed neural network (STPINN) as the solver for EM analysis. By coupling the physics-based EM analysis with dynamic temperature incorporating Joule heating and via effect, we can observe stress evolution along multisegment interconnect trees under constant, time-dependent, and space–time-dependent temperature during the void nucleation phase. The proposed STPINN method obviates the time discretization and meshing required in conventional numerical stress evolution analysis and offers significant computational savings. Numerical comparison with competing schemes demonstrates a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$52\times $ </tex-math></inline-formula> speedup with a satisfactory accuracy.

Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7 nm FINFET Technology for MIMO Applications

Full adders are a core component and play an essential role in the design of contemporary very-large-scale integration (VLSI) integrated circuits. Low-power, high-speed adder design has been the subject of numerous different sorts of research. The never-ending process is still in progress. The saturation point for MOS-based VLSI circuit design has been reached. As a consequence, many additional issues arise when MOS devices are scaled down to the nanoscale range, including an increase in leakage power and a vulnerability to PVT variation. Hence, MOSFET alternatives have been looked after by VLSI industries. Future nanoscale VLSI circuits would benefit greatly from the use of FINFETs in place of MOS transistors. In this paper, two diode-connected transistors-based low power, high speed, and low-power–delay product (PDP) adiabatic logic full adders are proposed using 7 nm technology. DCT TSAA-I, DCT TSAA-II, DCT TCAA-I, and DCT TCAA-II are the names of the proposed structures. Power, speed, and power–delay product (PDP) performance of the proposed adders are compared with those of traditional full adders. According to the simulation outcomes, the proposed adder architectures offer the least PDP in comparison to the adders taken into consideration. On power and delay, the impact of changing variables like temperature, supply voltage, load capacitance, and frequency is seen. A 7 nm FINFET model has been used in the simulations, which were conducted using the Hspice simulation tool.

An Online Course Content for Undergraduate Students on Full-Custom Design of a Digital VLSI Circuit Using Open-Source Software

The Very Large-Scale Integration (VLSI) circuit design is a promising field for undergraduate students hoping to explore job opportunities in electronics circuit design companies. Therefore, several institutes in India offer VLSI courses to electronics engineering undergraduate students. In recent times, because of the pandemic, online classes appeared as an effective method of teaching; this helped in running of academic schedule smoothly without hampering the students’ learning process. In this paper online teaching content is presented to help the student learn digital VLSI circuit design using an open-source tool. This course content is particularly helpful in understanding the theoretical and practical design of a Complementary Metal Oxide Semiconductor (CMOS)-based logic function, with minimal effort by the faculty without access to campus software. The content starts with a digital logic function and its switch-level representation into PULL-UP and PULL-DOWN networks. Then the switch-level circuit with the help of Euler’s graph is translated into a stick diagram and then converted into a layout cell using the lambda design rule. An interesting approach to choosing the gate sequence in the stick diagram from Euler’s graph, and the simulation result of the layout cell are presented and discussed. The approach helped the students in understanding full custom CMOS logic function design, test, and validation, with less effort and time. The survey shows that 86% of the students were satisfied with the content and that the course content helped to achieve an 81% average pass percentage in the two online semesters.

Specially-Designed Out-of-Order Processor Architecture for Microcontrollers

In very large-scale integration circuit (VLSI) systems, microcontrollers are often implanted to manage the whole system to complete the given computing tasks. They play an essential part as regulators, which should allocate resources steadily and issue instructions promptly to drive functional units. However, most of the recent research focuses on the operation at the software level or the scheduling at the SoC level, ignoring the impact of the microarchitecture and the features of controlled sub-modules. This paper analyzes the requirements of microcontrollers in the VLSI system with various constraints and conditions that should be considered in the hardware implementation of such microarchitecture. Furthermore, this paper takes an open-source design using RISC-V ISA as the prototype to implement hardware microarchitecture. This design integrates the techniques of out-of-order processing, which are usually used on superscalar processors. As a result, the design quadruples the number of pipelined instructions, greatly alleviating the stalling of the instruction stream with a maximum extra look up table utilization of 18.37% in FPGA implementation.

Recurrent deep neural learning classification algorithm based high level synthesis in VLSI circuit with runtime adaptability

Electronics industry has attained huge development in last few decades due to the rapid increase in system design applications. With the growth of very large scale integration (VLSI) design, integrated circuits (ICs) are employed in many applications. VLSI design comprises many steps like system-level design, high-level synthesis (HLS), logic design, test generation, and physical design. HLS interprets behavior description and create digital hardware that executes the behavior. But, the power-process-voltage-temperature (PPVT) variation can causee many issues and reduce the performance of VLSI design circuits. In order to address these problems, Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for better runtime adaptability with minimal time consumption. VLSI circuits are designed with the behavioral input and the output performance is measured at runtime. The behavioral description of the circuit is taken as input. Then, source code compilation process translates high level specification into Intermediate Representation (IR) and converts to control/data flow graph (CDFG). CDFG reveals data and control dependencies between operations. The proposed Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for providing better runtime adaptability with minimal time consumption. Finally, Register Transfer Level Generation is carried out to yield better runtime adaptability with minimal time. Simulation results on ISCAS’89 Benchmark Dataset, shows that the RDNLC-HLS model increases the FUSA with minimal error rate and CAT.

A Review on Low Power VLSI Design Models in Various Circuits

Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.

Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors

Since spiking neural networks (SNNs) can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale SNNs requires a simple and versatile silicon neuron model framework. In this article, a spiking neuron circuit as the core device of SNNs is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas–Niebur (MN) mathematical model is adopted. The improved MN model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.

An Accelerated Mixed-Height Cell Circuit Legalization Method

In Very Large-Scale Integration Circuit (VLSI) advanced node design, the standard cells are usually designed with mixed height to meet various requirements. In this paper, benefit from the initial placement from global placement, we first align cells to the power rail type matching rows and divide multi-row-height cells into single-row-height ones. Next, quadratic programming model is constructed and converted into linear complementarity problem (LCP). Last, we choose two matrix splits and apply an accelerated modulus-based matrix splitting iteration method to solve LCP. Experimental results indicate that we achieve better performance than two published state-of the-art works.

Modification and Characterization of Interfacial Bonding for Thermal Management of Ruthenium Interconnects in Next-Generation Very-Large-Scale Integration Circuits.

Ruthenium may replace copper interconnects in next-generation very-large-scale integration (VLSI) circuits. However, interfacial bonding between Ru interconnect wires and surrounding dielectrics must be optimized to reduce thermal boundary resistance (TBR) for thermal management. In this study, various adhesion layers are employed to modify bonding at the Ru/SiO2 interface. The TBRs of film stacks are measured using the frequency-domain thermoreflectance technique. TiN and TaN with high nitrogen contents significantly reduce the TBR of the Ru/SiO2 interface compared to common Ti and Ta adhesion layers. The adhesion layer thickness, on the other hand, has only minor effect on TBR when the thickness is within 2-10 nm. Hard X-ray photoelectron spectroscopy of deeply buried layers and interfaces quantitatively reveals that the decrease in TBR is attributed to the enhanced bonding of interfaces adjacent to the TaN adhesion layer, probably due to the electron transfer between the atoms at two sides of the interface. Simulations by a three-dimensional electrothermal finite element method demonstrate that decreasing the TBR leads to a significantly smaller temperature increase in the Ru interconnects. Our findings highlight the importance of TBR in the thermal management of VLSI circuits and pave the way for Ru interconnects to replace the current Cu-based ones.

LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION

Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

DETECTION OF POTENTIALLY UNRELIABLE VLSI BASED ON THE ANALYSIS OF TEMPERATURE-SENSITIVE PARAMETERS

The paper discusses methods for non-destructive diagnostic testing of very large scale integration circuits (VLSI) based on the “junction-case” thermal resistance parameter. This parameter is important because VLSI’s failure rate depends on junction temperature, which in turn depends on thermal resistance “junction-case”. There are three known methods for detecting potentially unreliable VLSIs with increased thermal resistance value: 1) non-destructive measurement of thermal resistance; 2) scanning acoustic microscopy; 3) an approach based on the statistical analysis of temperature-sensitive electric parameters. The paper presents advantages and disadvantages of each method. Special attention is paid to statistical analysis of temperature-sensitive electric parameters because this method allows detecting of potentially unreliable VLSIs without using expensive equipment. This method does not require changes in existing measurement programs. Electric parameters, which depend on temperature, are temperature-sensitive parameters. These parameters are useful for detecting VLSIs with deviations from the main batch. This allows decreasing of risk of potentially unreliable VLSIs application in high reliable equipment. With the proposed approach the high reliable equipment lifetime can be increased.

An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing

With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Gate Array (FPGA). First of all, this paper proposes an optimized dual-channel data storage and access method, so that the two-dimensional data access efficiency can be improved. Then, a hardware architecture is designed with register manager, simplified address generator and dual-channel Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) access mode. Finally, the proposed data controller is implemented on the Xilinx XC7VX690T FPGA chip. The experimental results show that the reading efficiency of the data controller proposed is 80% both in the range direction and azimuth direction, and the writing efficiency is 66% both in the range direction and azimuth direction. The results of a comparison with the recent implementations show that the proposed data controller has a higher data bandwidth, is more flexible in its design, and is suitable for use in spaceborne scenarios.

WITHDRAWN: Effectiveness of device parameters with regard to the electrical characteristics of the MOSFET double gate

The diminishment of metal-oxide semiconductor field-effect transistors (MOSFETs) is the sole reason to which made fabrication and integration of very large scale integrated circuits (VLSI) possible. The drastically reducing dimensions led a way to the devices with high density chips. Beside the advantages allied with the shortening of devices, it also has specific limitations usually identified as short-channel effects. The features move away from their expected values because of these effects. In order to minimize these deviations many techniques are introduced. These days a Multi-Gate (MG) transistor in VLSI is one of the encouraging and promising techniques. One of the MG transistors mostly used is Double-Gate (DG) transistor. Substrate is surrounded by gates from its either sides in DG MOSFET. So that, the gate terminal has more control over the electrons travelling in the channel. In the present work, investigation will be done on the effect of alteration of several device parameters on the DG MOSFET’s electrical characteristics. From the results, one can recognize the impact of change in the measurements and/or property of material on the electrical properties. To determine the maximum current related to those measurements of DG MOSFETs, these results will be very beneficial.

Вычисление коэффициента ускорения испытаний на безотказность на основе тепловизионного анализа кристалла сверхбольших интегральных схем

A new approach for evaluating the acceleration factor of forced reliability tests of very large scale integrated circuits (VLSI) is presented. The approach is based on subjecting the VLSI chip to an infrared image analysis. Currently, the VLSI reliability testing acceleration factor is evaluated based on the Arrhenius law, according to which this factor depends on the chip temperature. The chip temperature, in turn, is represented by the sum of the chip package temperature and the product of the maximum dissipated power and the chip-to-package thermal resistance. The drawback of the existing method is that the calculation is carried out for only a single chip temperature value that was obtained analytically. But the VLSI is a complex system, and it is not correct to judge about the testing acceleration factor proceeding from a single chip temperature value. It is proposed to calculate the VLSI reliability testing acceleration factor based on the temperatures at many points on the VLSI chip surface. This will make it possible to take into account the test sequence influence on the temperature distribution over the chip surface, thereby helping select the test sequences so that to obtain the maximal and uniform chip heating. Owing to the proposed method, it becomes possible to evaluate the testing acceleration factor more accurately and also to potentially increase it by choosing the test sequence. A more accurate evaluation of the acceleration factor allows the reliability tests reliability to be improved. The proposed method for evaluating the acceleration factor was validated experimentally. The workplace is described, the calculations of the reliability testing acceleration factors using two approaches are carried out, and their comparison is given.

Design of a new BUS for low power reversible computation

Optimization of device power can be achieved using reversible logic computation and this technique can be applied to a variety of low power applications such as optical computing, nanotechnology, Complementary Metal Oxide Semiconductor (CMOS), Very Large-Scale Integrated Circuits (VLSI) design and many more. Basic and universal gates are the elementary building blocks of digital system. In this paper, a new reversible Basic, Universal and Special (BUS) gate is proposed that is available as a single gate with multiple functionalities as basic (AND, OR & NOT), universal (NAND & NOR) and special gate (EXOR). The proposed BUS gate is implemented on Field Programmable Gate Array (FPGA) and simulated using 180 nm and 90 nm CMOS process technologies. Manchester adder and C17 circuit of ISCAS’85 (International Symposium on Circuits and Systems-1985) benchmark suite using BUS gate are designed and verified using Electronic Design Automation (EDA) tools. There is a power reduction of about 64.41% and 14.06% at 180 nm and 90 nm CMOS process technologies respectively in reversible BUS gate as compared to conventional CMOS-based designs. Thus, this paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems with low power dissipation.