Abstract
In Very Large-Scale Integration Circuit (VLSI) advanced node design, the standard cells are usually designed with mixed height to meet various requirements. In this paper, benefit from the initial placement from global placement, we first align cells to the power rail type matching rows and divide multi-row-height cells into single-row-height ones. Next, quadratic programming model is constructed and converted into linear complementarity problem (LCP). Last, we choose two matrix splits and apply an accelerated modulus-based matrix splitting iteration method to solve LCP. Experimental results indicate that we achieve better performance than two published state-of the-art works.
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