High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop

Abstract

With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.