Abstract
The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.
Highlights
Over the past half century the economics of the semiconductor industry have been driven by the principle of Moore’s law, which is really the observation that as semiconductor manufacturing technology continually improves the minimum manufacturing cost per device is continually decreasing and is realized by doubling the number of devices per square unit area roughly every two years [1]
This review summarizes some of the emerging applications for High K dielectrics which may be implemented in future semiconductor manufacturing
If Physical Vapor Deposition (PVD) can no longer be used due to the high aspect ratio of the Complementary Metal Oxide Semiconductor (CMOS) structure, it has already been shown that these layers can be deposited by Atomic Layer Deposition (ALD), with the added benefit of enabling Vt layers to be inserted within the HfO2 gate dielectric for lower thermal budget [47,48,49]
Summary
Over the past half century the economics of the semiconductor industry have been driven by the principle of Moore’s law, which is really the observation that as semiconductor manufacturing technology continually improves the minimum manufacturing cost per device is continually decreasing and is realized by doubling the number of devices per square unit area roughly every two years [1]. In order to continue device scaling to the 45 nm and below nodes, semiconductor device makers have implemented High K and Metal Gate (HKMG) stacks within the Metal Oxide Semiconductor Field. Representative examples of High K dielectrics include Al2O3, HfO2, ZrO2, HfZrO4, TiO2, Sc2O3 Y2O3, La2O3, Lu2O3, Nb2O5, Ta2O5 and simple mixtures thereof. By replacing dielectrics such as SiO2 (K = 3.9) and SiON (K = 4–6) with High K dielectrics, CMOS and DRAM manufacturers were able to continue scaling the Equivalent Oxide Thickness (EOT) of their devices while simultaneously using a physically thicker dielectric resulting in a leakage current reduction versus the. The potential to use High K dielectrics, and Al2O3, for patterning applications is examined
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