Very Large Scale Integration Chips Research Articles

Very Large-Scale Integration for Premature Ventricular Contraction Detection Using a Convolutional Neural Network

We propose a very large-scale integration (VLSI) chip for premature ventricular contraction (PVC) detection. The chip contains a convolutional neural network (CNN) for detecting the abnormal heartbeats associated with PVCs in 12-lead electrocardiogram signals. The proposed CNN comprises two convolutional layers and a fully connected layer; in testing, it achieved a high PVC detection accuracy of [Formula: see text]. Created by using a [Formula: see text]-[Formula: see text]m CMOS process, the developed chip consumes [Formula: see text] mW with a clock frequency of 50 MHz and gate count of [Formula: see text] K. Compared with the previously designed VLSI chips, the proposed CNN chip achieves higher accuracy in abnormal heartbeat detection.

An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

This paper proposes a time-domain analog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, our circuits use transient operation in charging/discharging processes to capacitors through resistors. Since the circuits calculate multiple weighted-sums by charging a capacitance, they can be operated with extremely low energy consumption. However, because a relatively long time constant is required to guarantee calculation resolution in the time domain, they have to use very high-resistance devices, on the order of giga-ohms. We designed, fabricated, and tested a proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using a 250-nm fabrication technology to verify weighted-sum operation based on the proposed model with binary weights and PWM input signals, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors, unlike in the ordinary in-memory-computing circuits. We evaluated the energy efficiency and temperature characteristics by measurement using the fabricated chip, where the highest energy efficiency for the weighted-sum calculation was 300 TOPS/W (Tera-Operations Per Second per Watt). The effects by a temperature change can be compensated for by adjusting the bias voltage. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible.

A comparison study of harmony search and genetic algorithm for the max-cut problem

Abstract The max-cut problem is one of well-known NP-complete problems and has applications in various fields such as the design process for VLSI (Very-Large-Scale Integration) chips and spin glass theory in statistical physics. In this paper, a harmony search algorithm for the max-cut problem is proposed. Compared to genetic algorithm, harmony search algorithm has advantages of generating a new vector after considering all of the existing vectors and requiring only a few number of parameters to be determined before the run of the algorithm. For 31 benchmark graphs of various types, the proposed harmony search algorithm is compared with a newly developed genetic algorithm and another genetic algorithm taken from the recent literature are presented. The proposed harmony search algorithm produced significantly better results than the two genetic algorithms.

Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

Analytical Modeling of Electromigration Failure for VLSI Interconnect Tree Considering Temperature and Segment Length Effects

Electromigration (EM) is a major concern for very large-scale integration (VLSI) interconnect reliability, particularly for interconnect trees with multibranch metal wires representing continuously connected metal (Cu) lines terminated at diffusion barriers. For EM modeling and assessment, one important problem is to perform fast EM time to failure analysis for practical VLSI chips. Compact modeling for EM effects for the interconnect tree has been studied recently to better EM signoff analysis. But the existing method cannot consider wires stressed under time-varying temperature, which is very typical for practical chip working conditions. In this paper, we develop the exact analytic model for the stress evolution of interconnect trees under different current density and varying segment length from the first principle. Due to the difficulty in obtaining the exact analytical solution, we focus on three-terminal wire in this paper. The stress evolution is modeled by two Korhonen’s equations coupled through boundary conditions which are solved with the Laplace transformation technique. The new analytical EM model is further extended to consider the time-varying temperature stressing condition and initial non-zero residual stress. The proposed method is compared with the finite-element method (FEM) tool COMSOL, the recently proposed eigenfunction-based method, and the published EM simulator XSim. The comparison shows that the analytical solution agrees well with the results from the FEM numerical analysis. It uses much fewer terms compared to the eigenfunction method for the same accuracy. It also agrees very well with XSim, which is consistent with the previously reported measured results.

S-visibility problem in VLSI chip design

Abstract: In this paper, a new version of very large scale integration (VLSI) layouts compaction problem is considered. Bar visibility graph (BVG) is a simple geometric model for VLSI chip design and layout problems. In all previous works, vertical bars or other chip components in the plane model gates, as well as edges, are modeled by horizontal visibilities between bars. In this study, for a given set of vertical bars, the edges can be modeled with orthogonal paths known as staircases. Therefore, we consider a new version of bar visibility graphs (BsVG). We then present an algorithm to solve the s-visibility problem of vertical segments, which can be implemented on a VLSI chip. Our algorithm determines all the pairs of segments that are s-visible from each other.

S-visibility problem in VLSI chip design

In this paper, a new version of very large scale integration (VLSI) layouts compaction problem is considered. Bar visibility graph (BVG) is a simple geometric model for VLSI chip design and layout problems. In all previous works, vertical bars or other chip components in the plane model gates, as well as edges, are modeled by horizontal visibilities between bars. In this study, for a given set of vertical bars, the edges can be modeled with orthogonal paths known as staircases. Therefore, we consider a new version of bar visibility graphs (BsVG). We then present an algorithm to solve the s-visibility problem of vertical segments, which can be implemented on a VLSI chip. Our algorithm determines all the pairs of segments that are s-visible from each other.

Analytical Modeling and Characterization of Electromigration Effects for Multibranch Interconnect Trees

Electromigration (EM) in very large scale integration (VLSI) interconnects has become one of the major reliability issues for current and future VLSI technologies. However, existing EM modeling and analysis techniques are mainly developed for a single wire. For practical VLSI chips, the elemental EM reliability unit called interconnect tree is a multibranch interconnect segment consisting of a continuously connected, highly conductive metal (Cu) lines terminated by diffusion barriers and located within the single level of metallization. The EM effects in those branches are not independent and have to be considered simultaneously. In this paper, we demonstrate, for the first time, a first principle-based analytical solution of this problem. We have derived the analytical expressions describing the hydrostatic stress evolution in several typical interconnect trees: 1) the straight-line three-terminal wires; 2) the T-shaped four-terminal wires; and 3) the cross-shaped five-terminal wires. The new approach solves the stress evolution in a multibranch tree by de-coupling the individual segments through the proper boundary conditions (BCs) accounting the interactions between different branches. By using Laplace transformation technique, analytical solutions are obtained for each type of the interconnect trees. The analytical solutions in terms of a set of auxiliary basis functions using the complementary error function agree well with the numerical analysis results. Our analysis further demonstrates that using the first two dominant basis functions can lead to 0.5% error, which is sufficient for practical EM analysis.

Data Intelligent Low Power High Performance TCAM for IP-Address Lookup Table

This paper represents current research in low-power Very Large Scale Integration (VLSI) domain. Nowadays low power has become more sought research topic in electronic industry. Power dissipation is the most important area while designing the VLSI chip. Today almost all of the high speed switching devices include the Ternary Content Addressable Memory (TCAM) as one of the most important features. When a device consumes less power that becomes reliable and it would work with more efficiency. Complementary Metal Oxide Semiconductor (CMOS) technology is best known for low power consumption devices. This paper aims at designing a router application device which consumes less power and works more efficiently. Various strategies, methodologies and power management techniques for low power circuits and systems are discussed in this research. From this research the challenges could be developed that might be met while designing low power high performance circuit. This work aims at developing Data Aware AND-type match line architecture for TCAM. A TCAM macro of 256 × 128 was designed using Cadence Advanced Development Environment (ADE) with 90 nm technology file from Taiwan Semiconductor Manufacturing Company (TSMC). The result shows that the proposed Data Aware architecture provides around 35% speed and 45% power improvement over existing architecture.

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.

A hybrid multi-objective PSO algorithm with local search strategy for VLSI partitioning

Very large scale integration (VLSI) circuit partitioning is an important problem in design automation of VLSI chips and multichip systems; it is an NP-hard combinational optimization problem. In this paper, an effective hybrid multi-objective partitioning algorithm, based on discrete particle swarm optimzation (DPSO) with local search strategy, called MDPSO-LS, is presented to solve the VLSI twoway partitioning with simultaneous cutsize and circuit delay minimization. Inspired by the physics of genetic algorithm, uniform crossover and random two-point exchange operators are designed to avoid the case of generating infeasible solutions. Furthermore, the phenotype sharing function of the objective space is applied to circuit partitioning to obtain a better approximation of a true Pareto front, and the theorem of Markov chains is used to prove global convergence. To improve the ability of local exploration, Fiduccia-Matteyses (FM) strategy is also applied to further improve the cutsize of each particle, and a local search strategy for improving circuit delay objective is also designed. Experiments on ISCAS89 benchmark circuits show that the proposed algorithm is efficient.

A NEW PLATFORM FOR THE IMPLEMENTATION OF REGULAR ITERATIVE ALGORITHMS INTO FPGAs

The implementation of regular iterative algorithms (RIAs) in important scientific fields such as image processing, computer arithmetic, cryptography and their implementation in processor arrays architectures, has been extensively studied over the last three decades. Numerous design methodologies and tools have been proposed, mostly targeting custom very large scale integration (VLSI) chips. The advent of field-programmable gate arrays (FPGAs) has attracted many researchers to incorporate previously acquired knowledge and experience in designing VLSI chips, to this new technology. This paper addresses the issue of the implementation of regular algorithms into FPGAs and presents a novel design tool for the implementation of RIAs, formulated as dependence graphs (DGs), on systolic arrays. Furthermore, a platform scheme for the systolic arrays hardware realization is proposed.

Neuromorphic Silicon Neurons and Large-Scale Neural Networks: Challenges and Opportunities

Neuromorphic silicoN NeuroNs: state of the art Complementary metal-oxide-semiconductor (CMOS) transistors are commonly used in very-large-scale-integration (VLSI) digital circuits as a basic binary switch that turns on or off as the transistor gate voltage crosses some threshold. Carver Mead first noted that CMOS transistor circuits operating below this threshold in current mode have strikingly similar sigmoidal current– voltage relationships as do neuronal ion channels and consume little power; hence they are ideal analogs of neuronal function (Mead, 1989). This unique device physics led to the advent of “neuromorphic” silicon neurons (SiNs) which allow neuronal spiking dynamics to be directly emulated on analog VLSI chips without the need for digital software simulation (Mahowald and Douglas, 1991). In the inaugural issue of this Journal, Indiveri et al. (2011) review the current state of the art in CMOS-based neuromorphic neuron circuit designs that have evolved over the past two decades. The comprehensive appraisal delineates and compares the latest SiN design techniques as applied to varying types of spiking neuron models ranging from realistic conductancebased Hodgkin–Huxley models to simple yet versatile integrate-and-fire models. The timely and much needed compendium is a tour de force that will certainly provide a valuable guidepost for future SiN designs and applications.

Thermal Dynamics of Multicore Integrated Systems

This paper presents an analysis of thermal dynamics in multicore systems, focusing on time response to heat generated in a single core and its connection with very large scale integration (VLSI) design principles. For the purpose of this paper, a point heating time (PHT) concept is introduced. PHT is a value that describes the time of temperature growth to its limited value. The PHT value is used for estimating the thermal capabilities of multicore systems. The physical properties of VLSI systems are taken into account for determining easy-to-apply rules of thermal dynamic response in common chip designs. The authors compare PHT in different physical conditions and its value versus displacement of the active thermal module away from the center position on the chip. An equation derived from analytical assumptions is the basis for asynchronous control of core activity toward minimizing its peak temperature. Final analysis leads to the conclusion that the paper can be used as a supplementary guide in VLSI chip development for better thermally optimized multicore chips.

A PSO-based intelligent decision algorithm for VLSI floorplanning

Floorplanning is an important issue in the very large-scale integrated (VLSI) circuit design automation as it determines the performance, size, yield and reliability of VLSI chips. This paper proposes a novel intelligent decision algorithm based on the particle swarm optimization (PSO) technique to obtain a feasible floorplanning in VLSI circuit physical placement. The PSO was applied with integer coding based on module number and a new recommended value of acceleration coefficients for optimal placement solution. Inspired by the physics of genetic algorithm (GA), the principles of mutation and crossover operator in GA are incorporated into the proposed PSO algorithm to make this algorithm to break away from local optima and achieve a better diversity. Experiments employing MCNC and GSRC benchmarks show that the proposed algorithm is effective. The proposed algorithm can avoid local minimum and performs well in convergence. The experimental results of the proposed method in this paper can also greatly help floorplanning decision making in VLSI circuit design automation.

The effect of mismatch in current‐ versus voltage‐mode resistive grids

AbstractResistive grids are commonly used in neuromorphic very large‐scale integration (VLSI) designs for image smoothing and signal aggregation. Because mismatch is inevitable in VLSI chips, one reason that resistive grids are attractive is that their output is robust to mismatch in the component values. Here, we examine relative sensitivity of different resistive grid designs that differ depending upon whether the input and output are represented by current or voltage. Our analysis reveals that a mixed‐mode design, where the input is represented by current but the output is represented by voltage, is less sensitive to mismatch when the amount of smoothing is large. On the other hand, when little smoothing is desired, pure voltage‐mode and current‐mode designs are preferred. From the point of view of mismatch sensitivity, there is little difference between the two pure‐mode designs. Our analysis also reveals that the difference in mismatch sensitivity is due to the vertical resistors, which are the most sensitive to mismatch in all the three designs studied. Copyright © 2008 John Wiley & Sons, Ltd.

An Introduction to Logic Circuit Testing

An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References

Silicon Photonics

After dominating the electronics industry for decades, silicon is on the verge of becoming the material of choice for the photonics industry: the traditional stronghold of III-V semiconductors. Stimulated by a series of recent breakthroughs and propelled by increasing investments by governments and the private sector, silicon photonics is now the most active discipline within the field of integrated optics. This paper provides an overview of the state of the art in silicon photonics and outlines challenges that must be overcome before large-scale commercialization can occur. In particular, for realization of integration with CMOS very large scale integration (VLSI), silicon photonics must be compatible with the economics of silicon manufacturing and must operate within thermal constraints of VLSI chips. The impact of silicon photonics will reach beyond optical communication-its traditionally anticipated application. Silicon has excellent linear and nonlinear optical properties in the midwave infrared (IR) spectrum. These properties, along with silicon's excellent thermal conductivity and optical damage threshold, open up the possibility for a new class of mid-IR photonic devices

Practical approach to gradient direction sensor method in very large scale integration thermomechanical stress analysis

Silicon integrated sensors for thermomechanical stress measurement in very large scale integration (VLSI) has been studied extensively in recent years due to the increasing complexity of modern semiconductor devices. As the chip size has increased continuously to accommodate more functions in modern integrated circuits (IC) technology, the stress induced in it from packaging combined with self-heating becomes serious and may result in the device degradation, circuit malfunction, and even chip cracking. Therefore, for large VLSI devices safe operation, it is necessary to construct in situ thermomechanical stress sensors to control the spatial induced peak stress. In this article, a practical approach to the application of a gradient direction sensor (GDS) for thermomechanical stress prediction in microelectronic packaging is presented. The GDS method has been studied and analyzed for its applicability as inverse engineering problem that is capable to detect the thermomechanical stress. This study uses a thermal heat sources emplacement approach to estimate and predict stress of wafer scale integration (WSI) chip junction. Hence, the geometrical coordinates of the investigated source can be obtained by applying the gradient direction sensors. Then finite element method will be used to build models to validate thermal peaks prediction by GDS method. This way, the possibilities to minimize the thermal peaks in the critical surface areas for ball grid array packaged WSI devices will be explored. Furthermore, in microelectronic, one of the primary roles of IC packaging is to provide structural stability for the VLSI chip. Hence, several considerations have guided our study for a judicious placement of different sensors. That will enable us to establish the most homogeneous thermomechanical cartography. Subsequently, other alternatives for heat sources placement or distribution that are capable in reducing the level of thermomechanical stress will be developed.

Global routing by iterative improvements for two-layer ball grid array packages

In current very large scale integration (VLSI) circuits, there can be hundreds of required I/O pins. Ball grid array (BGA) packaging is commonly used to realize the huge number of connections between VLSI chips and printed circuit boards (PCBs). In this paper, the authors propose a global-routing method by iterative improvements for two-layer BGA packages. In their routing model, the global routing for each net is uniquely determined by a via assignment. The proposed global-routing method begins with an initial feasible via assignment and incrementally improves the via assignment to minimize the maximum wire congestion and the total wire length. In each iteration, a via assignment is improved by exchanging two adjacent vias or by moving vias one by one to their adjacent grids. The algorithm efficiently generates better global routes than initial routes with respect to wire congestion and total wire length.