VLSI Research Articles

Comparative Analysis of CMOS-based D-type Flip-Flop Architectures for High-Performance VLSI Applications Using 45-nm CMOS Technology

High performance VLSI (very large-scale integration) is an essential electronic technology required for space missions and scientific advancements. The only source of reliance for the VLSI designer is the data storage devices designated as flip-flops, which are widely used in semiconductor memory devices as well as for data processing and storage in the telecommunication fields. In this paper, the four D-type flip-flop architectures of CMOS-based D-type flip-flops, such as D-type flip-flops using traditional technology (DFF-T), D-type flip-flops with Demorgan’s law (DFF-DL), D-type flip-flops with transmission gates (DFF-TG), and D-type flip-flops with five transistors (DFF-F), have been designed and constructed. The analytical simulations of the schematics and equivalent layouts of these four architectures are implemented using 45-nm complementary metal-oxide-semiconductor (CMOS) technology. With cadence virtuoso design software, the performance investigation of the four D-type flip-flop architectures is compared in terms of layout area, transistor counts, average power consumption, rise time, fall time, and propagation delay. The DFF-F technologies have modestly compact design goals in order to reduce production costs and achieve faster processing speeds with fewer transistors.

Comparative Analysis of High Speed and Area Efficient Full-Adder using CMOS and MGDI Techniques

Extremely quick processing is crucial for very large-scale integrated (VLSI) circuits in the arithmetic logic unit. Complementary metal oxide semiconductor (CMOS) and modified gate diffusion input (MGDI) are beneficial technologies for designing high-speed circuits with better reliability and performance with regard to area and power consumption. This research work provides a comparative performance analysis of a full adder that is implemented with CMOS and MGDI technology. This work aims to develop a CMOS-based full-adder and a MGDI-based full-adder circuit for area-efficient and high-speed applications. First, the analysis and implementation of the XOR and NAND logic gates are designed using CMOS technology and the MGDI technique to create a full-adder design. The comparative analysis of integrated circuits in CMOS and MGDI technologies is primarily determined by the number of transistors and delay time. The full-adder is designed and analyzed using 90 nm technology, with performance characteristics evaluated using Cadence Virtuoso Tools.

Implementation of a Reverse Carry Propagate Adder Based On Efficient VLSI for Hardware Security and Area Consumption

The various techniques inbuilt in the VLSI (Very Large Scale Integration) designing is originated from the basis of adder circuits. When these adder circuits are processed in the higher digital signal processing systems, the adders have to exhibit high performance, good efficiency with reduced cost and area of implementation. The major objective of designing the VLSI design is minimizing the complexity and to perform the operations more effectively. Whereas in some other methods, the logic circuit designing is made larger in order to achieve higher efficiency. This in turn, results in the reduction of hardware security and makes the computation more complex. This paper utilizes the RCPA adder logic to reduce the area for the implementation and enhancing the hardware security. By implementing RCPA adder circuit, the carry propagates in the opposite direction from the most significant bit to the least significant bit. The usage of shift accumulator improves the speed of process and reduces the area required. By implementing the reverse propagation of the carry in the adder circuit, computation time is optimized and the implementation is made efficient with the reduction in the delay.

Area-energy optimized ternary multiplier usingefficient design approaches in GNRFET technology

The semiconductor industry has long benefited from CMOS transistors in realizing advanced VLSI circuits. However, achieving area-energy optimization in CMOS-based VLSI circuits has become increasingly challenging due to short-channel effects. Another obstacle in manufacturing these transistors is the adoption of body-biasing techniques to adjust the threshold voltage (Vth) for developing ternary logic-based circuits. Researchers are now exploring emerging devices like graphene nanoribbon field-effect transistors (GNRFET) as potential candidates for future electronics. GNRFET devices not only leverage graphene’s remarkable properties but also benefit from the ability to achieve distinct Vth through tuning the width of graphene nanoribbons. This paper focuses on using tri-state 32-nm GNRFET devices to implement a novel area-energy optimized ternary multiplier circuit. To attain a logic ‘1′ in the proposed circuit, a power-efficient voltage division technique is employed. Additionally, efficient design approaches are used to reduce the critical path length and decrease the number of necessary transistors. Simulation results using HSPICE demonstrate that the proposed design reduces energy consumption by a minimum of 6.75% and up to 37.50% compared to other state-of-the-art 32-nm GNRFET-based TMUL circuits. Furthermore, the proposed design decreases both the area and complexity by utilizing a single-VDD and incorporating 24 transistors.

Freeform metasurface color router for deep submicron pixel image sensors.

Advances in imaging technologies have led to a high demand for ultracompact, high-resolution image sensors. However, color filter-based image sensors, now miniaturized to deep submicron pixel sizes, face challenges such as low signal-to-noise ratio due to fewer photons per pixel and inherent efficiency limitations from color filter arrays. Here, we demonstrate a freeform metasurface color router that achieves ultracompact pixel sizes while overcoming the efficiency limitations of conventional architectures by splitting and focusing visible light instead of filtering. This development is enabled by a fully differentiable topology optimization framework to maximize the use of the design space while ensuring fabrication feasibility and robustness to fabrication errors. The metasurface can distribute an average of 85% of incident visible light according to the Bayer pattern with a pixel size of 0.6 μm. The device and design methodology enable the compact, high-sensitivity, and high-resolution image sensors for various modern technologies and pave the way for the advanced photonic device design.

Squaring Circuit Using 14nmFinFET Technology with Vedic Mathematics Approach

FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively.

Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.

Optimization research of handwritten digit recognition algorithm based on hardware neural networks

In the modern era of digitization, the widespread application of handwritten numerical data has led to an exponential increase in data volume, necessitating efficient real-time recognition and processing systems. This project is grounded in the foundational structure of neural networks, with a specific focus on integrating these networks into hardware through Very-Large-Scale Integration (VLSI). The primary objective is to achieve faster processing speeds, lower power consumption, and real-time operations. The central emphasis of this study is the design and implementation of a hardware neural network system tailored specifically for handwritten digit recognition. Drawing from neural network theory, we explore the construction of a hardware-based handwritten digit classifier. The fundamental model employed is the single-layer perceptron neuron model. Upon receiving 28x28 pixel grayscale images, the image classifier utilizes pre-trained weights, activation functions, and a maximum selector to compare and output recognition results for numerical digits. The concrete implementation is realized using the Verilog hardware description language, coupled with algorithm optimization strategies to enhance performance and efficiency. This research endeavor aims to provide an effective hardware solution for real-time handwritten digit recognition in the digital age.

Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency

Previous work has presented a synthesizable design approach to ease the design of an on-chip period-jitter sensor (PJS) with a high resolution. Although the designer of a very large scale integration (VLSI) chip hopes to use this design as an intellectual property (IP), our analysis reveals that this PJS faces key challenges: high power consumption and vulnerability to static PVT and dynamic IR-drop variations. This work develops several design techniques to conquer these challenges at the same time. Taking the PJS IP for monitoring the clock signal in LPDDR4-4266 as a design example, we implement a synthesized 22 nm 2.133 GHz PJS with a resolution of 1.0 ps to verify the design techniques. Post-layout simulation results show that the new design reduces over half of the power while meeting the resolution specification. It passes functional and electrical verification over a broader process variation than the previous design, and the higher variation resiliency assists the synthesizable Verilog code as a soft IP.

An Efficient Design of 2-BIT Arithmetic Logical Unit in Quantum Dot Cellular Automata

For the past two decades, CMOS technology has reigned supreme in the world of Very Large Scale Integration (VLSI). But Quantum Dot Cellular Automata (QCA) is stepping into the spotlight, offering a fresh solution to the growing challenges of CMOS. This paper delves into the potential of QCA circuits by presenting a 2-bit Arithmetic Logic Unit (ALU) crafted with this groundbreaking technology, while also benchmarking it against conventional CMOS designs. The proposed QCA-based ALU delivers a trifecta of benefits: streamlined circuit design, exceptional space efficiency, and reduced quantum cost—all while keeping performance sharp in terms of latency and area usage. This 2-bit ALU encompasses a suite of operations: addition, subtraction, multiplication, division, bitwise AND, OR, XOR, and XNOR. QCA technology addresses some of CMOS's major pain points, like slow switching speeds, and doesn't require additional power sources, making it both efficient and environmentally friendly. This is not just an incremental improvement; it's a bold leap into the future of circuit design

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits

Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits

Investigating the Impact of Technology Scaling on Stability Performance of Sub-threshold Static Random Access Memory Bitcell Topologies

Static random-access memory (SRAM) is increasingly being used in VLSI circuits as a result of the development of portable devices. As the demand for low-power devices increases, sub-threshold operation of SRAMs has become a popular method to reduce power consumption but at the cost of reduced stability. The work aims to propose design parameters for SRAM bit cell topologies- 6T and 10T with proper device sizing and to investigate the impact of technology scaling on its stability performance in the sub threshold region. Moreover, analysis demonstrates the impact of variations of device sizing in terms of Cell ratio and Pull up ratio on stability margins of designed SRAM topologies. Simulations are carried out in the HSPICE environment using 16 nm and 22 nm CMOS process nodes. We find that the stability margins of 10T SRAM cell outperform the 6T SRAM cell; however stability margin decreases with decreasing technology nodes. The Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) of 10T SRAM cell is improved by 48.38% and 308.64% respectively in 22nm and 53.04% and 243.93% respectively in 16nm process technology as compare to 6T SRAM cell.

Design and analysis of an efficient low power low delay low leakage clock keeper domino logic

The design and development of CMOS VLSI semiconductor circuits employing deep sub-micron technology has faced significant challenges, primarily in terms of propagation delay and power consumption. This work introduces a new method called low leakage clock keeper domino logic (LLCKDL) for creating CMOS logic gates. The purpose of this approach is to decrease the amount of power consumed via leakage and enhance the efficiency of the gates in terms of noise. Existing and suggested methodologies can be employed to develop 16-bit input OR gates and simulated using GPDK 45 nm CMOS technological node in Cadence with a clock frequency of 10 MHz. The simulation results have been assessed by comparing the power usage, unity noise gain (UNG) and propagation latency. The Simulation outcomes show that the average power usage for the suggested domino has been improved to 87.12 %, 89.83 %, 93.38 %, 90.24 %, 86.4 %, and 88.01 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL and GPKD respectively. The delay for the suggested design has been improved to 42.66 %, 56.31 %, 29.97 %, 18.18 %, 11.25 %, and 16.95 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL, and GPKD respectively. The PDP for the suggested design has been improved to 92.62 %, 95.56 %, 95.37 %, 92.02 %, 87.94 % and 90.05 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL and GPKD respectively. The EDP for the suggested design has been improved to 95.78 %, 98.06 %, 96.76 %, 93.49 %, 89.28 % and 91.76 % concerning CEDL, CMFD, CSK-DL, HSCD, FDSTDL and GPKD respectively.

Qualitative data augmentation for performance prediction in VLSI circuits

Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180 nm and 22 nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog circuits and digital cells. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.

Advanced VLSI-based digital image contrast enhancement: A novel approach with modified image pixel evaluation logic

This research uses an extremely memory-intensive and power-efficient very-large-scale-integration (VLSI) architecture to perform nonlinear scaling on pictures. Images can be scaled either up or down so that they can be adapted to the differing resolutions of a variety of devices, such as cameras and printers. Photography with a high resolution calls for significantly more storage space and processing power. The branch of image processing known as “image fusion” has recently had a meteoric rise in prominence. The rapidly growing usage of digital imagery in remote sensing and satellite applications has led to an increase in the need to both store and process massive amounts of picture data. This demand has resulted in an increase in the availability of storage space. Traditional fusion methods produce spatial distortions despite their generally high level of spatial performance. Because of this, the discrete wavelet transformation (DWT), currently the most efficient approach for processing images, focuses on finding a solution to this problem. Within the scope of this investigation, we propose the modified image pixel evaluation logic (MIPEL), a functional method for incorporating the lifting-based strategy utilized in DWT-based picture fusion. In order to avoid excessive delays, high-resolution photo processing typically makes use of hardware processing, which necessitates the utilization of more complex apparatus and more time. In this work, the hardware description language verilog is employed to evaluate the effectiveness of various fundamental approaches to the enhancement of pictures. VHDL is a relatively recent method that has replaced more traditional simulations in the process of producing results for signal processing. It does this by allowing rapid access to physical VLSI representations. Utilizing the proposed MIPEL as a starting point, this study aims to design, model, simulate, and develop several different strategies for enhancing photos using FPGA. Because they take place on the pixel level and in the immediate neighborhood of a pixel, the enhancements that may be made to an image can be thought of as point processing procedures. VLSI architecture is developed for contrast augmentation for low-contrast source photos using pixel-based image fusion, and in the simulation results that followed, we offer findings that clearly illustrate the efficiency of this technology.

Crossing Number of Infinite Family of Extension Kochol's Periodic Graphs

At this time, technology is developing very quickly and is increasingly sophisticated. This technological development is certainly closely related to the development of computer technology. A computer is able to control a series of electronic devices using an IC chip that can be filled with programs and logic called microprocessor technology. A microprocessor is a digital component of the VLSI (Very Large Scale Integration) type with very high circuit complexity that is capable of carrying out the functions of a CPU (Central Processing Unit). Among many applications, the problem of crossing number very interesting and important because of its application in the optimization of chip are required in a circuit layout of VLSI. Crossing number used to obtain the lower bound on the amount of chip area of VLSI devices like microprocessor and memory chips additionally, crossings in the circuit layout could cause short circuit and therefore worth minimized independent of the chip area consideration. Some graph can be seen as built by small pieces. A principal tool used in construction of crossing-critical graphs are tiles. In the tile concept, tiles can be arranged by gluing one tile to another in a linear or circular fashion. The series of tiles with circular fashion form an infinite graph family. In this way, the intersection number of this family of graphs can be determined. In this research, has been formed an infinite family graphs The graph formed by gluing together many copies of the tile in circular fashion, where the tile consists of identical tile sections. The results obtained show that the graph has 3-crossing-critical of a graph.

The relationship between deformation mechanisms and mechanical properties in nanocrystalline Cu/Ag-bilayer alloy

The nanocrystalline metallic bilayer structure can effectively enhance the strength of Cu alloy while maintaining excellent electrical conductivity. Based on the microstructure evolution of Cu/Ag alloy observed by transmission electron microscope (TEM), molecular dynamics (MD) simulations of Cu/Ag alloy with nanocrystalline metallic bilayer structure were established. The mechanical properties and deformation mechanisms of nanocrystalline Cu/Ag-bilayer alloys were investigated at different temperatures. A mixed Hall-Petch (H-P) relationship was observed between the ultimate stress and the increased layer thickness. In this paper, the deformation mechanism changes from dislocation accumulation at the Cu-Ag interface to dislocation through the Cu-Ag interface. In addition, the data analysis results of elastic modulus showed an approximately linear decrease trend with increasing temperature, and the deformation mechanism shifted from dislocation motion to a combination of dislocation motion and grain boundaries (GBs) diffusion. These findings provide guidance for the design of high magnetic field facility (HMFF) water-cooled magnets and very large-scale integration (VLSI) lead frames.

A Case Study in VLSI Education during the COVID-19 Pandemic

COVID-19 presented numerous challenges to education. Many papers have been published detailing professors' successes and learning experiences in adapting their courses to the changing circumstances of the ongoing pandemic. For courses that have experienced great success, professors will likely choose to keep many of their remote elements. Over the past two years, we have had three capstone teams complete Very Large-Scale Integration (VLSI) designs in a remote environment, and while further improvements will be made going forward, we will continue with our fully remote course regardless of the currently loosening restrictions. We recently received our first undergraduate-led tape-out from fabrication and have begun preliminary testing.

Efficient very large-scale integration architecture design of proportionate-type least mean square adaptive filters

The effectiveness of adaptive filters are mainly dependent on the design techniques and the algorithm of adaptation. The most common adaptation technique used is least mean square (LMS) due its computational simplicity. The application depends on the adaptive filter configuration used and are well known for system identification and real time applications. In this work, a modified delayed μ-law proportionate normalized least mean square (DMPNLMS) algorithm has been proposed. It is the improvised version of the µ-law proportionate normalized least mean square (MPNLMS) algorithm. The algorithm is realized using Ladner-Fischer type of parallel prefix logarithmic adder to reduce the silicon area. The simulation and implementation of very large-scale integration (VLSI) architecture are done using MATLAB, Vivado suite and complementary metal–oxide– semiconductor (CMOS) 90 nm technology node using Cadence register transfer level (RTL) Genus Compiler respectively. The DMPNLMS method exhibits a reduction in mean square error, a higher rate of convergence, and more stability. The synthesis results demonstrate that it is area and delay effective, making it practical for applications where a faster operating speed is required.