Area-energy optimized ternary multiplier usingefficient design approaches in GNRFET technology

Abstract

The semiconductor industry has long benefited from CMOS transistors in realizing advanced VLSI circuits. However, achieving area-energy optimization in CMOS-based VLSI circuits has become increasingly challenging due to short-channel effects. Another obstacle in manufacturing these transistors is the adoption of body-biasing techniques to adjust the threshold voltage (Vth) for developing ternary logic-based circuits. Researchers are now exploring emerging devices like graphene nanoribbon field-effect transistors (GNRFET) as potential candidates for future electronics. GNRFET devices not only leverage graphene’s remarkable properties but also benefit from the ability to achieve distinct Vth through tuning the width of graphene nanoribbons. This paper focuses on using tri-state 32-nm GNRFET devices to implement a novel area-energy optimized ternary multiplier circuit. To attain a logic ‘1′ in the proposed circuit, a power-efficient voltage division technique is employed. Additionally, efficient design approaches are used to reduce the critical path length and decrease the number of necessary transistors. Simulation results using HSPICE demonstrate that the proposed design reduces energy consumption by a minimum of 6.75% and up to 37.50% compared to other state-of-the-art 32-nm GNRFET-based TMUL circuits. Furthermore, the proposed design decreases both the area and complexity by utilizing a single-VDD and incorporating 24 transistors.