Comparative Analysis of CMOS-based D-type Flip-Flop Architectures for High-Performance VLSI Applications Using 45-nm CMOS Technology

Abstract

High performance VLSI (very large-scale integration) is an essential electronic technology required for space missions and scientific advancements. The only source of reliance for the VLSI designer is the data storage devices designated as flip-flops, which are widely used in semiconductor memory devices as well as for data processing and storage in the telecommunication fields. In this paper, the four D-type flip-flop architectures of CMOS-based D-type flip-flops, such as D-type flip-flops using traditional technology (DFF-T), D-type flip-flops with Demorgan’s law (DFF-DL), D-type flip-flops with transmission gates (DFF-TG), and D-type flip-flops with five transistors (DFF-F), have been designed and constructed. The analytical simulations of the schematics and equivalent layouts of these four architectures are implemented using 45-nm complementary metal-oxide-semiconductor (CMOS) technology. With cadence virtuoso design software, the performance investigation of the four D-type flip-flop architectures is compared in terms of layout area, transistor counts, average power consumption, rise time, fall time, and propagation delay. The DFF-F technologies have modestly compact design goals in order to reduce production costs and achieve faster processing speeds with fewer transistors.