Investigating the Impact of Technology Scaling on Stability Performance of Sub-threshold Static Random Access Memory Bitcell Topologies

Abstract

Static random-access memory (SRAM) is increasingly being used in VLSI circuits as a result of the development of portable devices. As the demand for low-power devices increases, sub-threshold operation of SRAMs has become a popular method to reduce power consumption but at the cost of reduced stability. The work aims to propose design parameters for SRAM bit cell topologies- 6T and 10T with proper device sizing and to investigate the impact of technology scaling on its stability performance in the sub threshold region. Moreover, analysis demonstrates the impact of variations of device sizing in terms of Cell ratio and Pull up ratio on stability margins of designed SRAM topologies. Simulations are carried out in the HSPICE environment using 16 nm and 22 nm CMOS process nodes. We find that the stability margins of 10T SRAM cell outperform the 6T SRAM cell; however stability margin decreases with decreasing technology nodes. The Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) of 10T SRAM cell is improved by 48.38% and 308.64% respectively in 22nm and 53.04% and 243.93% respectively in 16nm process technology as compare to 6T SRAM cell.