Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Abstract

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.