A low power test pattern generation for built-in self-test based circuits

Abstract

A low-power test pattern generation, named the low switching activity test pattern generation (LSA-TPG), is proposed to reduce the power dissipation of built-in self-test (BIST)-based circuits during test. A single input changing (SIC) test pattern is generated by a counter and a Gray encoder which is called the SICG (single input changing generator). The built-in test vectors are generated by the SIC patterns which are exclusive-ORed with seeds generated by the modified linear feedback shift register (LFSR). All the test vectors are SIC patterns during the 2m test clock period; thus the switching activities of the test vectors are greatly reduced in test mode without compromising fault coverage. The proposed structure has the advantages of low test power and low hardware overhead. LSA-TPG is independent of circuit under test (CUT) and flexible enough to be used in both BIST and scan-based BIST architectures. The proposed architecture increases the correlation among the test patterns with negligible impact on test length. Experiments conducted on ISCAS'89 benchmark circuits demonstrate that the proposed scheme gives better fault coverage with a large reduction in test power dissipation.