An efficient test pattern generator for high fault coverage in built-in-self-test applications

Abstract

Built-In-Self-Test (BIST) has become one of the major test techniques for today's large scale and high speed designs. In this paper, a novel test pattern generator (TPG) for built-in-self-test is presented to attain the target fault coverage without increasing test length sequences. This proposed TPG method generates multiple patterns with single input change i.e., all vector applied to a scan chain is a single input change (SIC) vector. Hence, it reduces the number of transitions that occur at scan inputs during scan shift operations and also reduces the switching activity in the circuit under test (CUT). The linear feedback shift register (LFSR) is used to generate test patterns for primary inputs or scan chains input and a multiple input shift register (MISR) compresses test responses received from primary output or scan chains output. To test the fault coverage ratio of proposed test pattern generator a complicated Wallace tree multiplier circuit will be used as circuit under test and output response of Wallace tree multiplier is stored in LUT for error comparison. Simulation results with Wallace tree multiplier circuit demonstrate that MS IC can save test power by approximately 7% and achieves the target fault coverage by above 70% without increasing the test length sequences.