Very Fast Transmission Line Pulse Research Articles

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

Design of compact-diode-SCR with low-trigger voltage for full-chip ESD protection

In this article, a compact-diode-silicon-controlled rectifier (CDSCR) for full-chip electrostatic discharge (ESD) protection is proposed and verified in 0.18 μm Silicon-on-Insulator (SOI) Bipolar-CMOS-DMOS (BCD) process. Intrinsic parasitic SCRs and diodes are employed as the main ESD paths, which greatly reduces area consumption. Besides, due to the RC- triggered circuit, low trigger voltage and short turn-on time are realized. With equivalent circuit and two-dimensional (2D) technology computer-aided design (TCAD) simulation, the operation principle and working mechanism are analyzed. In addition, transmission line pulse (TLP) and very fast TLP (VF-TLP) testing results show that the CDSCR could can endure human body model (HBM) pulse of 3420 V without latch-up issue and protect the chip effectively in charge device model (CDM) event. Furthermore, the proposed structure exhibits high current handing ability during ESD stress conditions and sufficiently low leakage current during normal circuit operating conditions. The CDSCR is conformed to provide full-chip ESD protection for 1.2 V application.

Design of a NMOS-triggered SCR for dual-direction low-voltage ESD protection

An improved NMOS triggered dual-direction silicon controlled rectifier (NMOS-DDSCR) device is fabricated in 0.18 μm Silicon-on-Insulator (SOI) Bipolar-CMOS-DMOS (BCD) process. The proposed NMOS-DDSCR structure is designed based on the conventional DDSCR structure, which adds two additional auxiliary trigger paths achieved by NMOS transistors, diodes, and RC coupling circuits. The internal mechanism of NMOS-DDSCR is analyzed using two-dimension (2D) TCAD simulations, and the ESD performance is characterized by means of transmission line pulse (TLP) and very-fast TLP (VFTLP) measurements. Superior to the conventional DDSCR, the proposed NMOS-DDSCR exhibits a lower trigger voltage of 8.2 V, a higher human-body model (HBM) level of 4.0 kV, and a smaller leakage current of about 160 nA for low power application. In addition, the proposed NMOS-DDSCR has lower overshoot voltage, faster turn-on speed, and sufficient latchup immunity, which can be applied to ESD protection of 5.0 V input and output (I/O) pins in smart power integrated circuit (SPIC).

Novel dual-direction electrostatic discharge device with lateral PNP transistor

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge (ESD) as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are investigated. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in the DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than that of conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes the total triggering path of device shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than that of DDSCR. For thermal performance, most of the heat first accumulates near the lateral PNP transistor , and then the peak point of heat turns to main SCR path with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than that in DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Comparing with DDSCR, the conclusions are obtained. Under the condition of transmission line pulse (TLP) test simulation analyses, the triggering voltage is reduced by 31%, the holding voltage is increased by 16.8%, the ESD design window is optimized by 44.5%, and on-resistance is lower. When TLP stress is 2.67 A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed. When the VF-TLP stress is 0.1 A, the overshoot voltage of PNP_DDSCR device is the 37% of that of DDSCR device while the PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

ESD Design Verification Aided by Mixed-Mode Multiple-Stimuli ESD Simulation

Electrostatic discharge (ESD) protection is a grand design challenge for complex ICs in advanced technologies. ESD simulation is indispensable to guide ESD protection designs. However, no existing ESD simulation methods may accurately predict ESD protection designs in a universal manner due to various inherent limitations. TCAD-based ESD simulation is very useful for ESD protection designs. Transmission line pulse (TLP) and very fast TLP (VFTLP) are widely used to evaluate human body model (HBM) and charged device model (CDM) ESD protection designs, which provide rich details for calibrating TCAD ESD simulation for design prediction and validation. Using various ESD protection devices fabricated in 28nm CMOS and 45nm SOI CMOS technologies, a comprehensive experimental and simulation study finds that the ESD stimuli used in TCAD ESD design simulation have profound impacts on many subtle ESD protection behaviors, particularly in comparison with ESD testing. This study cautions against over-interpretation of TCAD ESD simulation results, obtained using any specific ESD stimulus, attempting to accurately predict practical ESD protection designs. A mixed-mode multiple-stimuli ESD simulation method is therefore developed to address the ESD stimulus induced ESD performance variation, hence offering a technique to achieve ESD protection design prediction.

TCAD Simulation Study of ESD Behavior of InGaAs/InP Heterojunction Tunnel FETs

For the first time, we investigated the electrostatic discharge (ESD) behavior of an InGaAs/InP heterojunction tunneling field effect transistor (HTFET). The device structure in this study has a high on-state current without extra process steps. Under the positive transmission line pulse (TLP) simulation, the band-to-band tunneling (BTBT) current acts as an important initial current to accelerate the occurrence of impact ionization and the device is turned on quickly. Under the negative transmission line pulse (TLP) simulation, the operating principle of the HTFET is the same as for a poly-bounded diode. The ESD robustness of the device under TLP simulation are evaluated, and the impact factors, with regard to ESD robustness and failure mode, are discussed. Finally, the device behavior under very fast transmission line pulse (VFTLP) simulations with different rise times and pulse widths is also investigated. The results show that this device may be used for the ESD protection of next-generation III–V technology.

A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS

Transient voltage peaking under very fast electrostatic discharge (ESD), like charged device model (CDM) pulse, is a serious problem to integrated circuits (ICs). A combined TCAD simulation and very fast transmission line pulse (VFTLP) testing method is proposed to thoroughly investigate the transient voltage peaking phenomena of diode-based ESD protection structures under CDM stressing. The study of a set of diode, diode-string and diode-triggered silicon-controlled rectifier (DTSCR) ESD protection structures, fabricated in a 28nm CMOS process, reveals that the inductive impedance along the ESD discharging path may be the root cause of voltage peaking under CDM stressing. The observation provides the design insights overcoming the voltage peaking problem in ESD protection designs before complicate CDM package level testing.

A compact LDMOS DDSCR for HV ESD protections with high robustness and reliability

The LDMOS-based silicon controlled rectifier (SCR) is commonly used in high voltage (HV) electrostatic discharge (ESD) protection due to its great current handling capability per area and HV protection ability. In this paper, an improved LDMOS-based dual direction SCR (LDMOS-DDSCR) device is designed by replacing floating N+ region with electrically-connected P+, N+ and P+ regions to enhance its ESD robustness, which is verified in a 0.5-μm (1p2m) 18 V HV CDMOS process. The internal mechanism of the proposed device is analyzed using two-dimension (2D) TCAD simulations, and the ESD performance is characterized by means of transmission line pulse (TLP) and very-fast TLP (VFTLP) measurements. Compared with the conventional LDMOS-DDSCR, the failure current of the compact LDMOS-DDSCR raises from 2.00 A to 4.02 A (increased by 101%), and the trigger voltage reduces from 44.28 V to 39.76 V, without sacrificing layout area. Furthermore, the TLP I-V curves of the proposed LDMOS-DDSCR are measured at different temperatures ranging from 25 °C to 125 °C, which proves its reliability and show potential use in the applications of high voltage integrated circuits.

Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection

A conventional diode-triggered silicon-controlled rectifier (DTSCR) structure with a layout strategy for electrostatic discharge (ESD) protection is presented and confirmed in a 65-nm CMOS technology. The modified device is featured by a scaled-down trigger-diode string, which shortens its turn-on time using a variable scaling factor. To confirm the parasitic resistance adjustments of the modified DTSCR, transmission line pulsing (TLP)/very fast transmission line pulsing (VF-TLP) tests and simulations are performed on the device. Compared to a conventional DTSCR, this structure exhibits an improved turn-on speed and robustness, which are suitable for I/O protection of ESD events in the nanosecond range, particularly the charged-device model (CDM) event.

Low trigger voltage bulk FinFET silicon controlled rectifier in nanotechnology

The bulk fin field-effect transistor (FinFET) has been the primary semiconductor technology in nanotechnology. To protect low supply voltage circuits based on FinFET, trigger voltage [Formula: see text] of the silicon controlled rectifier (SCR) which acts as electrostatic discharge (ESD) protection device should be lowered further. In this paper, in order to lower the [Formula: see text] an extra implant technique is proposed to form bridging well low trigger voltage FinFET SCR (FinFET BRLVTSCR). The experiments demonstrate that the trigger voltage can be lowered effectively. Moreover, the TCAD simulations bring an in-depth physical understanding of ESD current conduction and failure mechanism during ESD protection. Finally, the turn-on characteristic demonstrates proposed novel SCRs are fast and effective under TLP and very fast TLP (VFTLP) stress.

Investigation of layout effects in diode-triggered SCRs under very-fast TLP stress through full-size, calibrated 3D TCAD simulation

Electrostatic discharge (ESD) protection devices in advanced state-of-the-art CMOS technologies need to be optimized towards minimizing size and capacitive loading of the core circuitry without loss of ESD performance. In this work, a layout study of diode-trigged SCR (DTSCR) by means of calibrated 3D TCAD is presented. The focus lies on layout dependent uniformity of operation, and transient turn-on behaviour under very-fast (vf)-TLP stress, for which a 3D approach is mandatory. In this context, we employ a novel TCAD methodology that allows to reliably perform 3D process simulations in a fast, and yet accurate way. We can generate very large device structures with a mesh node count in the order of millions, such as the DTSCRs under investigation. Using rigorous 3D process simulation would be too expensive, or simply not feasible. Process simulation turnaround time (TAT) reduction from weeks to days or hours opens for the possibility of using the 3D TCAD simulation deck for guiding the layout optimization process.

A New On-Chip ESD Strategy Using TFETs-TCAD Based Device and Network Simulations

For the first time, this paper reports the quasi-static behavior and the applicability of the tunnel field effect transistor (TFET) for the on-chip electrostatic discharge (ESD) protection. ESD evaluations are performed on 28-nm fully depleted silicon-on-insulator (FDSOI), bulk TFET and compared with conventional shallow trench isolation (STI) diode using a well calibrated 3-D technology computer aided design (TCAD) device and process simulation deck. Initial design insights are obtained using the DC characteristics. The quasi-static behavior of a TFET is studied by applying transmission line pulsing (TLP) and very fast TLP (VFTLP) pulses at its drain terminal with gate shorted together and source connected to the ground. During negative TLP pulse at the drain, the TFET becomes a forward biased gated diode and exhibits reduced on-resistance compared to the STI diode. During positive TLP pulse, the tunneling current at the source-channel junction introduces a low impedance current path from drain to source compared to the blocking behavior of the STI diode. A short description of the advantages and challenges of the TFET from ESD perspective are also discussed. Finally, a new TFET ESD network is proposed and shown to exhibit multiple current paths compared to STI diode-based ESD network. From the network simulations, the proposed TFET-based ESD network is shown to exhibit better CDM response and hence providing a robust ESD solution for future system-on-chip design.

Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection

We report systematic transient characterization of a graphene ribbon (GR) used as an interconnect for electrostatic discharge (ESD) protection of future integrated circuits. A large set of GR wires (around 6000) with varying and practical dimensions were fabricated using the chemical vapor deposition method and characterized by transmission line pulsing (TLP) and very fast TLP (VFTLP) measurements. Comprehensive TLP and VFTLP testing with varying pulse rise time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{r})$ </tex-math></inline-formula> and duration ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{d})$ </tex-math></inline-formula> was performed across a wide temperature range ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T = -30/+110~^{\circ }\text{C}$ </tex-math></inline-formula> ). Measurement-based statistics reveal the relationship between ESD capability of GR wires and the wire length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L$ </tex-math></inline-formula> ), width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> ), and number of graphene layers, as well as ESD pulse shapes and operation temperature.

Evaluating the CDM-Robustness of the input buffer with very fast transmission line pulse

In this paper, a scheme for how to utilize VFTLP (very fast transmission line pulse) data to design an input buffer circuit for CDM (charged-device model) ESD protection is reported. The impedance of the ESD device under VFTLP stress is nearly 120Ω at the beginning of turn-on transient, and decreases with time toward 10Ω prior to the voltage falling below 0V. In this work, the fact that the dynamic-characteristic impedance of the ESD device under VFTLP testing is independent of the stress current is found. Since both VFTLP zapping and the CDM are nanosecond events, the dynamic-characteristic impedance of the ESD device can be used to evaluate the CDM threshold voltage of the input buffer based on the equivalent and simplified RLC circuit.

Design optimization of SiGe BiCMOS Silicon Controlled Rectifier for Charged Device Model (CDM) protection applications

Silicon Controlled Rectifier (SCR) devices fabricated in a SiGe BiCMOS technology are optimized for Charged Device Model (CDM) Electrostatic Discharge (ESD) protection. This optimization involves combined experimental and Technology Computer Aided Design (TCAD) ESD simulation analysis of the quasi-static current–voltage and transient response characteristics during fast stress conditions. The underlying physical mechanisms critical to the device design are demonstrated based on very fast transmission line pulsing (VFTLP) measurement and physics-based simulation results.

Study of graphene field‐effect transistors under electrostatic discharge stresses

Graphene field-effect transistors (GFETs) are characterised for the first time under electrostatic discharge stresses. The GFETs are measured from the transmission line pulsing (TLP) tester and very fast TLP (VFTLP) tester. The turn-on behaviour influenced by back gate voltage is investigated. The I-V curve of the GFETs shows no characteristic of snapback from TLP or VFTLP measurement.

Comparison of FICDM and Wafer-Level CDM Test Methods

The on-chip stresses induced by various charged device model (CDM) test methods are compared at both the package and wafer levels. Test methods studied include field-induced CDM (FICDM), wafer-level CDM (WCDM2), capacitively coupled transmission-line pulsing (CC-TLP), and very fast TLP (VF-TLP). The generated stresses are compared on the basis of voltage monitor readings and integrated circuit (IC) functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics can alter the externally measured FICDM current pulse relative to that delivered internal to the IC, causing miscorrelation with wafer-level testers.

ESD-Protected K-Band Low-Noise Amplifiers Using RF Junction Varactors in 65-nm CMOS

This paper presents two K-band low-noise amplifiers (LNAs) in 65-nm CMOS using the proposed RF junction varactors as the ESD protection devices. The junction varactors are customized for the RF ESD applications with accurate equivalent circuit models. The experimental results demonstrate excellent second breakdown currents (It2) and high ratios of the ESD level to parasitic capacitances (VESD/CESD) . Using the dual-diode topology, the first LNA demonstrates an over 2-kV Human-Body-Model (HBM) ESD protection level with a noise figure (NF) of 2.8 dB and a peak gain of 14.3 dB at around 24 GHz under a power consumption of only 7 mW. By incorporating an RF junction varactor as the extra gate-source capacitance at the input stage as a part of the ESD network, the second LNA presents an enhanced failure current level up to 2.6 A (corresponding to an HBM ESD level of 3.9 kV), and a Charge-Device-Model (CDM) ESD level up to 10.7 A, characterized by the Very Fast Transmission Line Pulse (VFTLP) tests. The second LNA shows a NF of 3.2 dB and a power gain of 13.7 dB, also under 7 mW.

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

Silicon-controlled rectifier (SCR) devices are used as local clamping ESD devices. However, conventional designs suffer from slow turn-on, which causes problems in sub 10 ns charged-device model (CDM) protection, especially in deeply scaled technologies. In this paper, a double-well field-effect diode (DWFED) and an improved field-effect diode (FED) are designed to address this challenge. They are fabricated and characterized in 45 nm silicon-on-insulator (SOI) technology and experimentally demonstrated to be suitable for pad-based local clamping under a normal supply voltage ( V dd) range (at or below 1 V) in high-speed applications. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests to predict the device performance in CDM events. FED’s advantages in improving transient turn-on behavior and reducing DC leakage current are analyzed and compared with the regular SCR and the DWFED. Technology CAD (TCAD) simulations are used to interpret turn-on behavior and guide design. The improved devices may be implemented in a local clamping scheme that expands the ESD design window for advanced technology nodes.

Evaluation of Transient Behavior of Polysilicon-Bound Diode for Fast ESD Applications

Transient behaviors of poly-bound diodes subject to pulses generated by the very fast transmission line pulsing (VFTLP) tester are characterized for fast ESD events such as the charged device model. The effects of changing a diode's dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and polygate configuration under the VFTLP stress is also investigated.