Abstract
A conventional diode-triggered silicon-controlled rectifier (DTSCR) structure with a layout strategy for electrostatic discharge (ESD) protection is presented and confirmed in a 65-nm CMOS technology. The modified device is featured by a scaled-down trigger-diode string, which shortens its turn-on time using a variable scaling factor. To confirm the parasitic resistance adjustments of the modified DTSCR, transmission line pulsing (TLP)/very fast transmission line pulsing (VF-TLP) tests and simulations are performed on the device. Compared to a conventional DTSCR, this structure exhibits an improved turn-on speed and robustness, which are suitable for I/O protection of ESD events in the nanosecond range, particularly the charged-device model (CDM) event.
Published Version
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