A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS

Chenkun Wang,Qi Chen,Fei Lu,Feilong Zhang,Cheng Li,Albert Wang

doi:10.1109/access.2020.2992496

Abstract

Transient voltage peaking under very fast electrostatic discharge (ESD), like charged device model (CDM) pulse, is a serious problem to integrated circuits (ICs). A combined TCAD simulation and very fast transmission line pulse (VFTLP) testing method is proposed to thoroughly investigate the transient voltage peaking phenomena of diode-based ESD protection structures under CDM stressing. The study of a set of diode, diode-string and diode-triggered silicon-controlled rectifier (DTSCR) ESD protection structures, fabricated in a 28nm CMOS process, reveals that the inductive impedance along the ESD discharging path may be the root cause of voltage peaking under CDM stressing. The observation provides the design insights overcoming the voltage peaking problem in ESD protection designs before complicate CDM package level testing.

Highlights

Continuous and aggressive scaling in CMOS technologies makes integrated circuits (ICs) at advanced nodes extremely sensitive to electrostatic discharge (ESD) failures [1]–[7]
This paper presents a comprehensive study of the transient voltage peaking effect observed in diode-based ESD protection structures under charged device model (CDM) ESD stressing
With the help of combined TCAD-very fast transmission line pulse (VFTLP) method, it is found that transient voltage peaking may be originated from the internal parasitic inductance along the ESD discharging path, from terminal to terminal through the inner intrinsic PN junction, of a diode-based ESD protection structure

Summary

INTRODUCTION

Continuous and aggressive scaling in CMOS technologies makes ICs at advanced nodes extremely sensitive to ESD failures [1]–[7]. The ultra-thin gates can be damaged by the super-fast CDM transient spikes, which is an emerging challenge in ESD protection designs for advanced ICs and becomes a sizzling research topic in the field [3]–[12]. Transient voltage peaking becomes a major CDM ESD protection design problem for ICs at sub-28nm nodes, which must be thoroughly understood. This paper presents a comprehensive study of transient voltage peaking of different diode-based ESD protection structures in 28nm CMOS under very fast ESD stressing, which was investigated using a new combined TCAD simulation and VFTLP testing method. C. Wang et al.: Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures.

VOLTAGE PEAKING IN DIODE ESD STRUCTURES

CONCLUSION