Vertical Interconnect Access Research Articles

Wearable and Comfortable e-Textile Headband for Long-Term Acquisition of Forehead EEG Signals

Electroencephalography (EEG) has a wide range of applications in medical diagnosis, and novel form of Human Machine Interfaces (HMI) for controlling prosthetic implants, wheelchairs, and home appliances in various forms of paralysis. However, the current EEG setups are composed of many wires hanging down from the system, and individual electrodes that must be set manually, which is time-consuming. As a result, the overall system is neither comfortable, nor aesthetically appealing. Here, we introduce for the first time, a comfortable textile-based EEG headband system that is soft, conformal to the skin, and comfortable. We present materials and methods for fabrication of multi-layer stretchable e-textile, that interfaces the human epidermis from one side through printed electrodes, and interfaces a rigid PCB island on the second layer. We as well demonstrate a method that allows creation of VIAs (vertical interconnect access) between the layers, using a CO2 laser. All Electrodes are integrated into the headband, and thus there is no need for individual electrode placement, and individual wiring. By screen printing a home-made conductive stretchable ink, patient-specific EEG headbands can be tailor made considering the optimal positioning of the electrodes for each patient. We show that these printed electrodes benefit from a very low skin-electrode impedance, comparable to gold standard Ag/AgCl, or gold cup electrodes, thanks to the high surface area silver flakes used in this work. The e-textile headband interfaces with an EEG acquisition device that captures, amplifies, and transmits the data to an external mobile phone or a PC. Furthermore, the integrated amplification in the textile and the use of an EMF rejection layer on top of the electrodes were shown to reduce the unwanted EM noise that is picked up by the system. We as well show application of the developed headband for usage in Human Machine Interfaces and Sleep Data Acquisition. Altogether, this device is step toward wider use of EEG acquisition devices for daily-use applications.

Vertically-Aligned Multi-Walled Carbon Nano Tube Pillars with Various Diameters under Compression: Pristine and NbTiN Coated.

In this paper, the compressive stress of pristine and coated vertically-aligned (VA) multi-walled (MW) carbon nanotube (CNT) pillars were investigated using flat-punch nano-indentation. VA-MWCNT pillars of various diameters (30–150 µm) grown by low-pressure chemical vapor deposition on silicon wafer. A conformal brittle coating of niobium-titanium-nitride with high superconductivity temperature was deposited on the VA-MWCNT pillars using atomic layer deposition. The coating together with the pillars could form a superconductive vertical interconnect. The indentation tests showed foam-like behavior of pristine CNTs and ceramic-like fracture of conformal coated CNTs. The compressive strength and the elastic modulus for pristine CNTs could be divided into three regimes of linear elastic, oscillatory plateau, and exponential densification. The elastic modulus of pristine CNTs increased for a smaller pillar diameter. The response of the coated VA-MWCNTs depended on the diffusion depth of the coating in the pillar and their elastic modulus increased with pillar diameter due to the higher sidewall area. Tuning the material properties by conformal coating on various diameter pillars enhanced the mechanical performance and the vertical interconnect access (via) reliability. The results could be useful for quantum computing applications that require high-density superconducting vertical interconnects and reliable operation at reduced temperatures.

Stretchable and Skin-Conformable Conductors Based on Polyurethane/Laser-Induced Graphene.

The conversion of various polymer substrates into laser-induced graphene (LIG) with a CO2 laser in ambient condition is recently emerging as a simple method for obtaining patterned porous graphene conductors, with a myriad of applications in sensing, actuation, and energy. In this paper, a method is presented for embedding porous LIG (LIG-P) or LIG fibers (LIG-F) into a thin (about 50 μm) and soft medical grade polyurethane (MPU) providing excellent conformal adhesion on skin, stretchability, and maximum breathability to boost the development of various unperceivable monitoring systems on skin. The effect of varying laser fluence and geometry of the laser scribing on the LIG micro–nanostructure morphology and on the electrical and electromechanical properties of LIG/MPU composites is investigated. A peculiar and distinct behavior is observed for either LIG-P or LIG-F. Excellent stretchability without permanent impairment of conductive properties is revealed up to 100% strain and retained after hundreds of cycles of stretching tests. A distinct piezoresistive behavior, with an average gauge factor of 40, opens the way to various potential strain/pressure sensing applications. A novel method based on laser scribing is then introduced for providing vertical interconnect access (VIA) into LIG/MPU conformable epidermal sensors. Such VIA enables stable connections to an external measurement device, as this represents a typical weakness of many epidermal devices so far. Three examples of minimally invasive LIG/MPU epidermal sensing proof of concepts are presented: as electrodes for electromyographic recording on limb and as piezoresistive sensors for touch and respiration detection on skin. Long-term wearability and functioning up to several days and under repeated stretching tests is demonstrated.

Optimization of the interconnect resistance contribution for STT-MRAM technology

STT-MRAM has emerged as versatile memory technology, capable of serving a broad range of memory applications. A key figure of merit for the STT-MRAM device is the tunneling magnetoresistance ratio (TMR), which distinguishes between the high resistance (“Off”) and low resistance (“On”) state. In an Integrated Circuit (IC), the MRAM device is fabricated in back-end-of-line process and is powered using a MRAM Vertical Interconnect Access (M-VIA) structure. The series resistance from M-VIA structure, however, adversely impacts the TMR reducing the sense margin. Thus, to improve the TMR/sense margin of MRAM device, reduction of series M-VIA resistance is necessary. We present a combination of ab-initio & TCAD simulations to estimate the M-VIA resistance contributions. Advanced interconnect metals, which include Co, Ru and W, are studied with TiN as barrier metal. The role of barrier metal and geometry is systematically investigated. These simulations provide potential pathways to reduce the M-VIA resistance contributions, allowing for a high density MRAM array.

Integrated multilayer stretchable printed circuit boards paving the way for deformable active matrix

Conventional rigid electronic systems use a number of metallization layers to route all necessary connections to and from isolated surface mount devices using well-established printed circuit board technology. In contrast, present solutions to prepare stretchable electronic systems are typically confined to a single stretchable metallization layer. Crossovers and vertical interconnect accesses remain challenging; consequently, no reliable stretchable printed circuit board (SPCB) method has established. This article reports an industry compatible SPCB manufacturing method that enables multilayer crossovers and vertical interconnect accesses to interconnect isolated devices within an elastomeric matrix. As a demonstration, a stretchable (260%) active matrix with integrated electronic and optoelectronic surface mount devices is shown that can deform reversibly into various 3D shapes including hemispherical, conical or pyramid.

Implementation of Metallic Vertical Interconnect Access in Hybrid Intercalated Graphene/Quantum Dot Photodetector for Improved Charge Collection

Colloidal quantum dots (QDs) are of great interest in optoelectronic and photovoltaic devices with low-cost processing, strong light absorption, and size tunable direct band gap. However, their limited carrier mobility and short diffusion length limit efficient charge collection and transport. The short diffusion length in QD solid films, 100–200 nm, limits their thickness to t≈200–300 nm, resulting in poor absorption in the near-infrared, lambda>800 nm, wasting part of sunlight and reducing power conversion efficiency. Recently, a novel architecture based on multiple graphene monolayers (Gr) intercalated inside QD films was reported to improve charge extraction beyond QDs diffusion length. The intercalated graphene layers ensure efficient charge collected in QD films thicker than the diffusion length. However, this architecture still fails to collect carriers from the QDs when the thickness is >200 nm due to the poor vertical conductivity of the devices. Herein, we present the fabrication, optimization and implementation of intercalated devices with vertical interconnecting contacts, increasing carrier collection and photocurrent, aiming to develop a novel architecture for improved photodetection and photovoltaics with QDs. First, we analyze the individual roles of Gr and QDs, studying the evolution of light absorption, photocurrent, and conductivity as successive QD and Gr layers are added. We find the optimal interspacing between graphene layers in the intercalated system, aiming for the best compromise between light absorption and efficient charge collection. Our main contribution is the implementation of vertical interconnect access (VIAs) to each graphene layer to ensuring efficient charge transfer from Gr to the gold electrical contacts for efficient current collection. We show that for 850 nm wavelength illumination, photocurrent of intercalated devices show a 10 fold improvement over devices without VIAs. We also use a back-gate voltage to monitor Fermi level shift in Gr and charge transfer from QDs to Gr. The intercalated configuration with VIAs contacts herein presented is a significant improvement in charge collection for QD optoelectronic applications as well as a promising architecture to enhance the power conversion efficiency for QD solar cells.

Reliable interfaces for EGaIn multi-layer stretchable circuits and microelectronics.

We tackle two well-known problems in the fabrication of stretchable electronics: interfacing soft circuit wiring with silicon chips and fabrication of multi-layer circuits. We demonstrate techniques that allow integration of embedded flexible printed circuit boards (FPCBs) populated with microelectronics into soft circuits composed of liquid metal (LM) interconnects. These methods utilize vertical interconnect accesses (VIAs) that are produced by filling LM alloy into cavities formed by laser ablation. The introduced technique is versatile, easy to perform, clean-room free, and results in reliable multi-layer stretchable hybrid circuits that can withstand over 80% of strain. We characterize the fabrication parameters of such VIAs and demonstrated several applications, including a stretchable touchpad and pressure detection film, and an all-integrated multi-layer electromyography (EMG) circuit patch with five active layers including acquisition electrodes, on-board processing and Bluetooth communication modules.

Modeling AOD-driven laser microvia drilling with machine learning approaches

Acousto-optic deflectors (AODs) have been used to extend the bandwidth of laser beam scanning frequency in order to meet the growing demand on the quality and throughput of creating micro-size vertical interconnect access or microvia in electronic packaging materials. The implementation of AOD offers unprecedented spatiotemporal flexibilities for the laser drilling process control, meanwhile increases complexity for modeling the process and predicting the process result. Design of experiment and analysis of variance can reveal connections between process parameters and responses, but are incapable of predicting results with sufficient accuracy for some of the highly nonlinear processes. In this article, multiple machine learning techniques, including k-Nearest Neighbor, decision tree, support vector machine, support vector regression and artificial neural networks, are explored and compared in predicting the result of AOD-driven drilling processes. Among these techniques, artificial neural network shows advantage on accuracy. For instance, a mean squared error of as low as 1.21 μm2 is achieved in predicting the top diameter of microvias drilled by a 6-parameter process. Thus the artificial neural network is proved an ideal solution for modeling laser applications controlled by multiple process parameters.

Mechanisms of Directed Self-Assembly in Cylindrical Hole Confinements

The directed self-assembly of block copolymers in cylindrical holes is a promising technology for lithographic patterning, particularly in the context of vertical interconnect accesses. While the hole-shrink process for single cylinders has been extensively explored, the proliferation of morphological defects remains a significant technological barrier. We use a coarse-grained model to explore morphologies that form within cylindrical confinements for combinations of template surface energies. We identify metastable defect morphologies, in addition to the desired cylindrical morphology, in majority-wetting sidewall templates. We use our coarse-grained model and the string method to identify transition pathways between defective morphologies and the cylindrical morphology to elucidate the mechanism of defect annihilation within the confinements; the transition pathway from a disordered state is also identified. This work demonstrates that the minimum free energy path for the formation of a cylinder goes th...

A New Printed Electronics Approach Eliminating Redundant Fabrication Process of Vertical Interconnect Accesses: Building Multilayered Circuits in Porous Materials

AbstractPrinted electronics are striving for smaller size, increased functionality, and lower energy consumption, which impose critical demand for multilayered printed circuits. As a low‐cost and green substrate, cellulose paper has become the most attractive choice for the printing of sustainable and disposable electronics. However, the redundant processes of drilling holes and/or depositing of dielectric materials, when fabricating the vertical interconnect access (VIA) for these multilayered circuits, greatly increase the cost. In this paper, a simple, cost‐effective, and scalable method is proposed for fabricating high‐performance, multilayered paper‐based circuits which contain highly conductive VIAs without physically drilling holes or depositing additional dielectric material. Taking advantages of inkjet printing and electroless copper deposition, the metallization depth of the substrate can be controlled with ease. In the proposed method, the porous structure of cellulose paper, which is previously an obstacle to printed electronics, becomes an advantage by triggering the 3D copper deposition, resulting in an ultralow sheet resistance of ≈4.8 mΩ sq−1 for single layer traces and ≈2.6 mΩ sq−1 for VIAs. A functional double‐layered and battery‐free device with drill‐less VIA, featuring an energy harvesting function, is fabricated using the proposed method on paper for the first time.

Inkjet Printed Wiring Boards with Vertical Interconnect Access on Flexible, Fully Compostable Cellulose Substrates

AbstractCellulose foil is a biodegradable and carbon neutral material that is a poor substrate for most conductive silver inks. Herein, it is reported that a simple solution of silver acetate in 1‐methylimidazole can be used to produce conductive patterns on a commercial packaging foil that is composed almost exclusively from cellulose. The reduction can be carried out thermally or by irradiation with UV light. In the latter case, the printed pattern may become conductive on both sides of the substrate and also exhibits conductivity across the cellulose foil, giving rise to fully printed vertical interconnect access. Control experiments confirm that the cellulose plays a crucial role in completing the reduction of the silver salt, obtaining conductive patterns.

A Single Droplet‐Printed Double‐Side Universal Soft Electronic Platform for Highly Integrated Stretchable Hybrid Electronics

Soft features in electronic devices have provided an opportunity of gleaning a wide spectrum of intimate biosignals. Lack of data processing tools in a soft form, however, proclaims the need of bulky wires or low‐performance near‐field communication externally linked to a “rigid” processor board, thus tarnishing the true meaning of “soft” electronics. Furthermore, although of rising interest in stretchable hybrid electronics, lack of consideration in multilayer, miniaturized design and system‐level data computing limits their practical use. The results presented here form the basis of fully printable, system‐level soft electronics for practical data processing and computing with advanced capabilities of universal circuit design and multilayer device integration into a single platform. Single droplet printing‐based integration of rigid islands and core–shell vertical interconnect access (via) into a common soft matrix with a symmetric arrangement leads to a double‐side universal soft electronic platform that features site‐selective, simultaneous double‐side strain isolation, and vertical interconnection, respectively. Systematic studies of island‐morphology engineering, surface‐strain mapping, and electrical analysis of the platform propose optimized designs. Commensurate with the universal layout, a complete example of double‐side integrated, stretchable 1 MHz binary decoders comprised of 36 logic gates interacting with 9 vias is demonstrated by printing‐based, double‐side electronic functionalization.

Computational study for reliability improvement of a circuit board

BackgroundAn electronic device consists of electronic components attached on a circuit board. Reliability of such a device is limited to fatigue properties of the components as well as of the board. Printed circuit board (PCB) consists of conducting traces and vertical interconnect access (via) out of copper embedded in a composite material. Usually the composite material is fiber reinforced laminate out of glass fibers and polyimid matrix. Different reasons play a role by choosing the components of the laminate for the board, one of them is its structural strength and fatigue properties. An improvement of board’s lifetime can be proposed by using computational mechanics.MethodsIn this work we present the theory and computation of a simplified one layer circuit board conducting electrical signals along its copper via, producing heat that leads to thermal stresses.ResultsSuch stresses are high enough to perform a plastic deformation. Although the plastic deformation is small, subsequent use of the electronic device causes accumulating plastic deformation, which ends the lifetime effected by a fatigue failure in the copper via.ConclusionComputer simulations provide a convenient method for understanding the nature of this phenomenon as well as predicting the lifetime. We present a coupled and monolithic way for solving the multiphysics problem of this electro-thermo-mechanical system, numerically, by using finite element method in space and finite difference method in time.

A novel design on ultra-thin lateral-current-injection III–V on silicon with ultra-compact optical VIA for heterogeneous electronic–photonic integration

A novel approach to integrate an ultra-thin and ultra-compact lateral-current-injection (LCI) III–V on silicon-on-insulator platform by direct wafer bonding technique is proposed and designed. The proposed LCI III–V on silicon platform has an ultra-thin thickness of 270 nm which is ~10 times thinner than the vertical current injection III–V bonded on silicon. It has a confinement factor in the 100 nm thick active region larger than 40 % for 1 µm wide III–V waveguide, which is the highest among all the other integration schemes proposed so far. An optical vertical interconnect access to transfer light efficiently between III–V and silicon layer is designed. The design of the shortest “Optical Via” of 4 µm which gives ~100 % coupling efficiency is presented.

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Propagation delay and power dissipation for different aspect ratio of single-walled carbon nanotube bundled TSV

Through-silicon vias (TSVs) have provided an attractive solution for three-dimensional (3D) integrated devices and circuit technologies with reduced parasitic losses and power dissipation, higher input-output (I/O) density and improved system performance. This paper investigates the propagation delay and average power dissipation of single-walled carbon nanotube bundled TSVs having different via radius and height. Depending on the physical configuration, a comprehensive and accurate analytical model of CNT bundled TSV is employed to represent the via (vertical interconnect access) line of a driver-TSV-load (DTL) system. The via radius and height are used to estimate the bundle aspect ratio (AR) and the cross-sectional area. For a fixed via height, the delay and the power dissipation are reduced up to 96.2% using a SWCNT bundled TSV with AR = 300 : 1 in comparison to AR = 6 : 1.

Heterogeneously integrated III-V laser on thin SOI with compact optical vertical interconnect access.

A new heterogeneously integrated III-V/Si laser structure is reported in this report that consists of a III-V ridge waveguide gain section on silicon, III-V/Si optical vertical interconnect accesses (VIAs), and silicon-on-insulator (SOI) nanophotonic waveguide sections. The III-V semiconductor layers are introduced on top of the 300-nm-thick SOI layer through low temperature, plasma-assisted direct wafer-bonding and etched to form a III-V ridge waveguide on silicon as the gain section. The optical VIA is formed by tapering the III-V and the beneath SOI in the same direction with a length of 50 μm for efficient coupling of light down to the 600 nm wide silicon nanophotonic waveguide or vice versa. Fabrication details and specification characterizations of this heterogeneous III-V/Si Fabry-Perot (FP) laser are given. The fabricated FP laser shows a continuous-wave lasing with a threshold current of 65 mA at room temperature, and the slope efficiency from single facet is 144 mW/A. The maximal single facet emitting power is about 4.5 mW at a current of 100 mA, and the side-mode suppression ratio is ∼30 dB. This new heterogeneously integrated III-V/Si laser structure demonstrated enables more complex laser configuration with a sub-system on-chip for various applications.

ANALYSIS OF A VERTICAL INTERCONNECTION ACCESS BY USING LONGITUDINAL WAVE CONCEPT ITERATVE PROCESS (LWCIP)

A new formulation of the Wave Concept Iterative Process (WCIP) method is presented in this work. This approach uses an analysis with the longitudinal components instead of the transverse components. This approach includes decomposing the transverse TM modes into two longitudinal terms: the TM and TEM modes. This approach is applied to model a Vertical Interconnect Access VIA hole. The current density behavior is studied in the two cases with and without VIA hole. Also this method is used to study a SIW slot antenna. Compared to those obtained by available published data, our results show that the proposed method gives convincing results.

Demonstration of heterogeneous III–V/Si integration with a compact optical vertical interconnect access

Heterogeneous III-V/Si integration with a compact optical vertical interconnect access is fabricated and the light coupling efficiency between the III-V/Si waveguide and the silicon nanophotonic waveguide is characterized. The III-V semiconductor material is directly bonded to the silicon-on-insulator (SOI) substrate and etched to form the III-V/Si waveguide for a higher light confinement in the active region. The compact optical vertical interconnect access is formed through tapering a III-V and an SOI layer in the same direction. The measured III-V/Si waveguide has a light coupling efficiency above ~90% to the silicon photonic layer with the tapering structure. This heterogeneous and light coupling structure can provide an efficient platform for photonic systems on chip, including passive and active devices.

Highly Conductive, Flexible, Polyurethane‐Based Adhesives for Flexible and Printed Electronics

AbstractFlexible interconnects are one of the key elements in realizing next‐generation flexible electronics. While wire bonding interconnection materials are being deployed and discussed widely, adhesives to support flip‐chip and surface‐mount interconnections are less commonly used and reported. A polyurethane (PU)‐based electrically conductive adhesive (ECA) is developed to meet all the requirements of flexible interconnects, including an ultralow bulk resistivity of ≈1.0 × 10−5 Ω cm that is maintained during bending, rolling, and compressing, good adhesion to various flexible substrates, and facile processing. The PU‐ECA enables various interconnection techniques in flexible and printed electronics: it can serve as a die‐attach material for flip‐chip, as vertical interconnect access (VIA)‐filling and polymer bump materials for 3D integration, and as a conductive paste for wearable radio‐frequency devices.