Vertical Interconnect Access Research Articles

Heterogeneous Si/III-V integration and the optical vertical interconnect access

A new heterogeneous Si/III-V integration and the optical vertical interconnect access to the silicon-on-insulator (SOI) nanophotonic layer is proposed and designed. The III-V semiconductor layers are directly bonded to the SOI layer and etched to form the Si/III-V waveguide (after removal of the substrate), which has no air-trench or SOI channel waveguide underneath as the prior art. The design example shows a 1.5 μm wide Si/III-V waveguide has a confinement factor of ~24% in a 100 nm-thick active region for effective light amplification/absorption. The optical vertical interconnect access is realized through tapering both the III-V semiconductor waveguide and SOI layer in the same direction. Optimization using a simple approximated two-dimensional modal presented gives ~100% coupling efficiency with a 25 μm long optical vertical interconnect access. A three-dimensional finite-difference-time-domain electromagnetic simulation verifies the design numerically and also shows the proposed structure has a good alignment tolerance for fabrication.

Low temperature substrate transfer technique for 3D vertically aligned carbon nanotube architectures

The integration of aligned carbon nanotubes (CNTs) into microstructured device architectures is of utmost interest to bridge the gap between the nano and micro size regime. This can be achieved by bundling these nanostructures to larger micro-sized arrays of aligned CNTs. Device applications of such CNT array structures can be envisaged, e.g., in field emission, sensors or in sub-µm vertical interconnect access application. However, high process temperatures which are typically used for the synthesis of CNTs are not always tolerable for an overall device integration process. Therefore, low temperature transfer techniques for as grown 3D aligned CNT arrays onto substrates different than the initial growth substrate are desirable. Here we propose a novel method to transfer 3D CNT block arrays containing vertically grown CNTs. The combination of flip-chip and micro-contact printing allows for a transfer of highly ordered CNT block arrays onto inorganic and organic substrates at temperatures as low as 100°C.

Coupling between Vias and the PCB Power-Bus

Abstract. In this paper, a method for the extraction of data for a through-hole vertical interconnect access (via) on a printed circuit board (PCB) is presented. It uses a matrix de-embedding algorithm and two-port theory to extract the elements of an assumed lumped via model. After that the influence of the via on the power-bus impedance and the coupling between the via and the power-bus are described using this model.

Laser-assisted processing of VIAs for AlGaN/GaN HEMTs on SiC substrates

Vertical interconnect accesses (VIAs) were fabricated between the source electrode on the front and the ground on the backside of high-power microwave AlGaN/GaN high-electron mobility transistors (HEMTs) on /spl sim/400-μm-thick silicon carbide substrates. Through-wafer microholes with an aspect ratio of up to /spl sim/ 8 were drilled using pulsed UV-laser machining and subsequently metallized using electroplating. The successful implementation of the laser-assisted VIA technology into device processing was proven by dc and RF characterization. When biased at 26 V, a saturated output power of 41.6 W with an associated power-added efficiency of 55% at 2 GHz was achieved for a 20-mm AlGaN/GaN HEMT with through-wafer VIAs.