Vertical Double-diffused Metal Oxide Semiconductor Research Articles

Novel SenseFET structure for VDMOS with adopting body reverse bias technique to adjust the reference current ratio

- Detecting current accurately and low-loss is an extremely important and challenging task in intelligent power switches. In the paper, the novel SenseFET structure, based on the Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) is proposed, which realizes variable reference current ratios by employing the body reverse bias technique. Several simulations are carried out, by using Sentaurus TCAD Software, to ensure that other performances of the sense transistor, with body reverse bias, are not affected. Compared to the constant reference current ratio, the new method improves the current sensing accuracy by 14% at 0.1 A, makes it easier to extract the targeted voltage by using a small reference current ratio at small load currents and reduces the power dissipation of the detection branch by using a large reference current ratio at large load currents. The structure, presented in this paper, provides the guiding methodology for a wide range of load current sensing and can be easily fabricated without adding additional mask.

Response of Commercial P-Channel Power VDMOS Transistors to Ionizing Irradiation and Bias Temperature Stress

In this paper, the effects of successively applied static/pulsed negative bias temperature (NBT) stress and irradiation on commercial p-channel power vertical double-diffused metal-oxide semiconductor (VDMOS) transistors are investigated. To further illustrate the impacts of these stresses on the power devices, the relative contributions of gate oxide charge ([Formula: see text]) and interface traps ([Formula: see text]) to threshold voltage shifts are shown and studied. It was shown that when irradiation without gate voltage is used, the duration of the pre-irradiation static NBT stress has a slightly larger effect on the radiation response of power VDMOS transistors. Regarding the fact that the investigated components are more likely to function in the dynamic mode than the static mode in practice, additional analysis was focused on the results obtained during the pulsed NBT stress after irradiation. For the components subjected to the pulsed NBT stress after the irradiation, the effects of [Formula: see text] neutralization and [Formula: see text] passivation (usually related to annealing) are more enhanced than the components subjected to the static NBT stress, because only a high temperature is applied during the pulse-off state. It was observed that in devices previously irradiated with gate voltage applied, the decrease of threshold voltage shift is significantly greater during the pulsed NBT stress than during the static NBT stress.

Novel Vertical Power MOSFET With Step Hk Insulator Close to Super Junction Limit Relationship Between Breakdown Voltage and Specific ON-Resistance by Improving Electric Field Modulation

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> (Hk) MOSFET concept in this article with the step high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42~\mu \text{m}$ </tex-math></inline-formula> . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

Capacitance–Voltage Technique Based on Time Varying Magnetic Field for VDMOSFET—Part II: Measurements and Parameter Extractions

In part I, we have proposed a new capacitance–voltage technique ${C}$ ( ${V}$ ), which is simultaneously based on external ac magnetic field for surface potential modulation and on dc voltage to sweep the gate voltage. In part II, we describe the parameter extractions of vertical double diffusion metal–oxide–semiconductor field effect transistor (VDMOSFET) devices, combining the capacitance characteristics of gate–source, ${C}_{\text {GS}}$ ( ${V}_{G}$ ) and gate–drain ${C}_{\text {GD}}$ ( ${V}_{G}$ ), measured using the above cited technique, with those measured conventionally. In doing so, we have been able to extract semiconductor capacitance ( ${C}_{\text {SC}}$ ), interface trap capacitance ( ${C}_{\text {it}}$ ), doping profile concentration ${N}$ ( ${x}$ ), and interface trap density ${D}_{\text {it}}$ ( ${E}$ ) of different regions of VDMOSFET.

Investigating the Failure Mechanism of Short-Circuit Tests in 1.2-kV SiC JBS-Integrated MOSFETs

In this article, the failure mechanism of a 1.2-kV monolithic junction barrier-controlled Schottky diode integrated silicon carbide metal–oxide–semiconductor field-effect transistor (JMOS) under short-circuit (SC) tests has been investigated by an experimental validation and simulation analysis. As a new type of device, JMOS has superior performance and chip area efficiency. However, the SC ruggedness of the JMOS needs further investigation. When comparing vertical double-diffused metal–oxide–semiconductor field-effect transistor (VDMOS) and JMOS devices in the SC test study, the leakage current of the JMOS is much higher than that of a common VDMOS. During the SC test, the JMOS drain current cannot be successfully suppressed after gate turn-off, and the thermionic emission current due to heat generation in the Schottky barrier diode (SBD) region continues flowing into the n-drift region. The SBD thermionic emission current is rapidly increased by the increasing lattice temperature, which can reach over 1600 K. Eventually, the JMOS undergoes thermal runaway due to positive electrothermal feedback. A mechanistic study was set up to analyze the relationship between the SC limit and the leakage current in the SBD region of the heated materials. Finally, the key to improve the SC ruggedness of the JMOS is decreasing the leakage current in the SBD region.

Breakdown Voltage Walk-in Phenomenon and Optimization for the Trench-Gate p-Type VDMOS Under Single Avalanche Stress

An anomalous breakdown voltage (BV) walk-in phenomenon of the trench-gate p-type vertical double-diffused metal–oxide–semiconductor (VDMOS) after single avalanche stress has been experimentally investigated. It is found that the BV of the VDMOS is decreased after the single avalanche stress, while other electrical parameters remain unchanged. T-CAD simulations and emission microscope (EMMI) analysis have been carried out. As a result, the shift of the breakdown point of the VDMOS, which results in the hot hole injection and trapping at the termination region, should be responsible for the BV degradation. A novel device structure with different trench depths in the termination region for the trench-gate p-type VDMOS is proposed to suppress the BV walk-in phenomenon.

Accumulation-Mode Device: New Power MOSFET Breaking Superjunction Silicon Limit by Simulation Study

In this article, new structures are proposed with an extra electrode for accumulation-mode vertical double-diffused metal-oxide semiconductor (VDMOS) (EA VDMOS) and a gate electrode for accumulation-mode VDMOS (GA VDMOS). For accumulation-mode VDMOS, the drift region is lightly doped to support drain voltage in the OFF-state. A large density of electrons is accumulated to modulate the conductivity of the drift region in the ON-state. It is contradictory to obtain high breakdown voltage (BV) and low specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ ) in the conventional VDMOS, because both of them depend on the doping concentration of the drift region. This contradictory relationship between the BV and ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ is eliminated for EA and GA VDMOS, thereby breaking the superjunction (SJ) silicon limit. Simulation results indicate that ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of the accumulation-mode VDMOS devices are significantly reduced. The ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of EA and GA VDMOS can be reduced by 60% (0.85 $\text{m}\Omega ~ \cdot $ cm2) and 30% (1.68 $\text{m}\Omega ~ \cdot $ cm2) compared with the SJ VDMOS (2.41 $\text{m}\Omega ~ \cdot $ cm2) at the BV of 600 V, respectively. In addition, the performance of the accumulation-mode VDMOS is independent of charge balance which is necessary for the SJ VDMOS.

Degradation of Radiation-Hardened Vertical Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor During Gamma Ray Irradiation Performed After Heavy Ion Striking

The combined impact of single event effect (SEE) and total ion dose (TID) on Si-based radiation-hardened Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) Field-Effect Transistor (VDMO-SFET) is investigated in this letter. As previous research of VDMOS on TID effect and SEE carried out separately, in fact, the combined impact could degrade the device performance more seriously, because of the greater numbers of oxide-trapped charges and interface states generated, which is more pronounced during multiple gamma irradiation and post-irradiation annealing. This phenomenon indicates that SEE is not only a transient effect, influencing whether the devices can be driven to failure, but also a potential threat to the long-term reliability of MOSFETs used in aerospace applications.

Displacement damage on P-channel VDMOS caused by different energy protons

In this paper, characteristics of displacement and ionization damage on P-channel VDMOS (Vertical double-diffused Metal Oxide Semiconductor) deceives caused by 3 MeV and 6 MeV protons were investigated. The key electrical parameters such as threshold voltage and leakage current are measured. Experimental results show that threshold voltage move to left shift and the leakage current increases. The electrical properties measurement is performed in-situ by 3 MeV and 6 MeV protons, and the changes of electrical properties are different. The shift of threshold voltage is higher for the 6 MeV protons than for the 3 MeV ones. The leakage current is higher after the irradiation by 3 MeV protons than it by the 6 MeV ones. Annealing at room temperature for 300 days leads to an obvious decrease in the shift of threshold voltage, and has a little effect on leakage current. The increase in leakage current is mainly caused by displacement and the ionization damage mainly changes the shift of threshold voltage.

Characteristics and reliability of VDMOS under capacitive loads

The failure mechanism of vertical double-diffusion metal-oxide-semiconductor (VDMOS) turning on under capacitive loads is analyzed. Due to the structural features of the device, it is easy to burnout at the source pad (SPAD) area when turning on under capacitive loads. On the basis of simulation, thermal characteristics of VDMOS devices under capacitive loads are analyzed. The results show that junction temperatures (Tj) are obviously affected by capacitive load values (CL) and thermal resistances (Rth) of VDMOS devices. When Rth = 0.1 °C/W or Rth = 0.15 °C/W, curves between Tj and CL present an approximately linear relationship, while when Rth = 0.2 °C/W, the rate of Tj rising with CL shows an increasing trend. At last, the influences of device structure and process on capacitive load limits are verified by experiments. The results show that the design of local oxidation of silicon (LOCOS) structure has little effect on capacitive load limits of devices, while the capacitive load limit of the fourth generation (R4) process devices is obviously higher than that of the fifth generation (R5) process devices.

Incorporation of hafnium and platinum metal in vertical power MOSFETs

A novel, vertical single-diffused metal–oxide–semiconductor (VSDMOS) structure is proposed by applying workfunction engineering to a vertical power metal–oxide–semiconductor field-effect transistor (MOSFET) with source and drain regions formed using the charge plasma concept. Electron and hole plasma was induced by employing hafnium and platinum metal. Furthermore, the electrical characteristics of the proposed VSDMOS were compared with those of conventional vertical double-diffused metal–oxide–semiconductor devices, revealing that the proposed VSDMOS exhibits a 14 % increase in current driving capability, with improved breakdown voltage.

High electric field stress model of n-channel VDMOSFET based on artificial neural network

In VDMOSFETs (Vertical Double-Diffused Metal-Oxide Semiconductor Field-Effect Transistor), in the cases when the voltage at the gate contact comes close to the breakdown voltage, a high electric field (HEF) is formed in the gate oxide. This leads to the generation of fixed and mobile charged defects in the gate oxide and at the silicon/oxide interface. The mechanisms of defects formation are very complex, so it is impossible to create a unique physical model that could describe the behavior of components, i.e., its electrical characteristics, depending on the stress voltage and the stress time. In cases like this, the application of artificial neural network (ANN) has proved to be one of the acceptable solution. In fact, this approach can give the very accurate models for the define range of changes of the input parameters, without going into very complex physical and chemical processes that occur in the structure of the components. All that is necessary to generate the ANN model is the sufficiently large number of the measured data and correct selection of the neural network structure and appropriate training algorithm. In this paper, we have applied the multilayer feedforward neural networks to the model of high electric field stress effects (HEFS) in the n-channel VDMOS power transistor. Experimentally measured transfer characteristics for different times of stress were used to train the neural networks of different configurations. In addition, the influence of several different training algorithms on the accuracy of the model was studied. It is shown that a properly selected neural network structure and training algorithm provide the ANN model of HEFS of the n-channel VDMOS power transistor that very precisely gives its electrical characteristics (transfer characteristic and threshold voltage) for a given stress voltage and temperature in the whole range of the time stress changes from 0 to 150 min.

Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal–oxide–semiconductor device with high-κ insulator**Project supported by the National Natural Science Foundation of China (Grant No. 61404110) and the National Higher-education Institution General Research and Development Project, China (Grant No. 2682014CX097).

An improved vertical power double-diffused metal–oxide–semiconductor (DMOS) device with a p-region(P1) and high-κ insulator vertical double-diffusion metal–oxide–semiconductor (HKP-VDMOS) is proposed to achieve a better performance on breakdown voltage (BV)/specific on-resistance (Ron,sp) than conventional VDMOS with a high-κ insulator (CHK-VDMOS). The main mechanism is that with the introduction of the P-region, an extra electric field peak is generated in the drift region of HKP-VDMOS to enhance the breakdown voltage. Due to the assisted depletion effect of this p-region, the specific on-resistance of the device could be reduced because of the high doping density of the N-type drift region. Meanwhile, based on the superposition of the depleted charges, a closed-form model for electric field/breakdown voltage is generally derived, which is in good agreement with the simulation result within 10% of error. An HKP-VDMOS device with a breakdown voltage of 600 V, a reduced specific on-resistance of 11.5 mΩ·cm2 and a figure of merit (FOM) (BV2/Ron,sp) of 31.2 MW·cm−2 shows a substantial improvement compared with the CHK-VDMOS device.

Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

The mechanisms responsible for the effects of consecutive irradiation and negative bias temperature (NBT) stress in p-channel power vertical double-diffused MOS (VDMOS) transistors are presented in this paper. The investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation.

A review of pulsed NBTI in P-channel power VDMOSFETs

Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide-semiconductor (MOS) devices simultaneously exposed to negative gate voltage and elevated temperature. In this study we provide overview of threshold voltage instabilities observed in commercial p-channel power vertical double-diffused MOS field-effect transistors (VDMOSFET) IRF9520 under the pulsed NBT stress conditions. These instabilities are caused by the NBT stress induced changes in oxide trapped charge and interface trap densities, and are more significant at higher voltages and/or temperatures. NBT stress induced degradation under the pulsed gate bias conditions is generally lower as compared to static stress. Less significant degradation of threshold voltage found after pulsed bias stressing is ascribed to the recovery effects. Partial recovery occurs during the low level of pulsed gate voltage as a consequence of the removal of recoverable component of degradation and is associated with passivation/neutralization of shallow oxide traps that have not been transformed into the deeper traps (permanent component). A specific approach has been applied in this study in order to assess the recoverable and permanent components of degradation in commercial p-channel power VDMOSFETs subjected to NBT stressing. Experimental data have been analysed in terms of the mechanisms responsible for changes in the densities of gate oxide charge and interface traps.

On‐resistance reduction in vertical double diffusion metal oxide semiconductor devices using stress applied by thin film

This work presents a novel method of reducing on-resistance (R on) in vertical double diffusion metal oxide semiconductor (VDMOS) devices using external stress. By electrodepositing a layer of nickel (Ni) film onto the surface of drain pad, intrinsic film stress is applied on the VDMOS chip. The experiment results show that R on was reduced by 1.7, 2.4, 4.5, 8.3 and 10.5% when the film stresses were 39.2, 49.3, 61.7, 71.6 and 80.3 MPa, respectively. Moreover, thermal stress between Ni film and VDMOS chip can further reduce R on when the temperature increases. Compared with conventional methods for R on reduction, this method is independent of fabrication process of VDMOS devices and capable of controlling accurately the applied stress.

Dislocation-Induced Punchthrough Causing Drain-to-Source Leakage Current in Power VD MOSFET Structures

A detailed characterization of the leakage in semiconductor devices is essential for proper adjustment of the manufacturing process in order to eliminate the leakage. Subsurface punchthrough was determined as the leakage current mechanism in the power vertical double-diffused metal–oxide–semiconductor field-effect-transistor, and the quadratic dependence of the drain current was confirmed for the leakage caused by the punchthrough. A failure analysis revealed a large number of dislocations located in the corners of transistor cells. The majority of the detected dislocations were electrically inactive. Dislocation depth measurement indicated that only a small number of the dislocations penetrated deep into the channel, i.e., penetrated from source area to the boron-doped p− transistor channel. The transistor channel shortening caused by the enhanced phosphorus diffusion along the dislocations was determined as the root cause of the leakage. The diffusion spikes of the phosphorus atoms lengthened the n+ source layer, and the interface of the n+ and p− layer was shifted into the transistor channel at the site of the dislocation. Manufacturing process experiments related to the channel lengthening and the channel doping confirmed the theory of the dislocation-induced channel shortening. The occurrence of dislocations was attributed to the surface stress induced by the improper conditions of oxide growing and plasma etching in the affected regions.

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

In this paper, we report the results of consecutive irradiation and negative bias temperature (NBT) stress experiments performed on p-channel power vertical double-diffused metal–oxide semiconductor transistors. The purpose is to examine the effects of a specific kind of stress in devices previously subjected to the other kind of stress, as well as to assess if possible the behavior of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to a further increase of negative threshold voltage shift due to additional build-up of both oxide trapped charge and interface traps. NBT stress effects in previously irradiated devices may, however, depend on gate bias applied during irradiation and on the total dose received: in the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress seems to lead to further device degradation, whereas in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress seems to have a positive role since it practically anneals a part of radiation-induced degradation.

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET**Project supported by the Fund from the Ministry of Education, Science and Technological Development of the Republic of Serbia (Grant Nos. OI-171026 and TR-32026) and the Ei PCB Factory, Niš.

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

Nondestructive measurement of thermal contact resistance for the power vertical double-diffused metal-oxide-semiconductor**Project supported by the National Natural Science Foundation of China (Grant No. 61204081).

To obtain thermal contact resistance (TCR) between the vertical double-diffused metal-oxide-semiconductor (VDMOS) and the heat sink, we derived the relationship between the total thermal resistance and the contact force imposed on the VDMOS. The total thermal resistance from the chip to the heat sink is measured under different contact forces, and the TCR can be extracted nondestructively from the derived relationship. Finally, the experimental results are compared with the simulation results.