Abstract
The failure mechanism of vertical double-diffusion metal-oxide-semiconductor (VDMOS) turning on under capacitive loads is analyzed. Due to the structural features of the device, it is easy to burnout at the source pad (SPAD) area when turning on under capacitive loads. On the basis of simulation, thermal characteristics of VDMOS devices under capacitive loads are analyzed. The results show that junction temperatures (Tj) are obviously affected by capacitive load values (CL) and thermal resistances (Rth) of VDMOS devices. When Rth = 0.1 °C/W or Rth = 0.15 °C/W, curves between Tj and CL present an approximately linear relationship, while when Rth = 0.2 °C/W, the rate of Tj rising with CL shows an increasing trend. At last, the influences of device structure and process on capacitive load limits are verified by experiments. The results show that the design of local oxidation of silicon (LOCOS) structure has little effect on capacitive load limits of devices, while the capacitive load limit of the fourth generation (R4) process devices is obviously higher than that of the fifth generation (R5) process devices.
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