Novel SenseFET structure for VDMOS with adopting body reverse bias technique to adjust the reference current ratio

Abstract

- Detecting current accurately and low-loss is an extremely important and challenging task in intelligent power switches. In the paper, the novel SenseFET structure, based on the Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) is proposed, which realizes variable reference current ratios by employing the body reverse bias technique. Several simulations are carried out, by using Sentaurus TCAD Software, to ensure that other performances of the sense transistor, with body reverse bias, are not affected. Compared to the constant reference current ratio, the new method improves the current sensing accuracy by 14% at 0.1 A, makes it easier to extract the targeted voltage by using a small reference current ratio at small load currents and reduces the power dissipation of the detection branch by using a large reference current ratio at large load currents. The structure, presented in this paper, provides the guiding methodology for a wide range of load current sensing and can be easily fabricated without adding additional mask.