Analysis of a Failure in High-Voltage VDMOS Device caused by Die Contamination

Abstract

Vertical double diffused metal oxide semiconductor (VDMOS) device is one of the most widely used power semiconductor devices. Multiple VDMOS devices for aerospace application failed after reliability tests. The device function was abnormal because drain-source breakdown voltage (BVDSS) and zero gate voltage leakage current (IDSS) were out of tolerance. Failure analysis and defect localization methods were utilized to determine the root cause of VDMOS failure. The causes of chip leakage were localized and analyzed by means of electrical test, infrared thermographic defect localization, superficial surface microscopic morphology observation, and chemical composition analysis. It was found that there was a small amount of contamination on the chip surface. The contaminant ions migrated into the inner chip, forming an inverted layer at the edge of the chip, and creating additional leakage channels. These factors lead to the chip failure. Compared with the conventional failure analysis method for VDMOS device, the comprehensive failure analysis method proposed in this study can directly locate defect point, observe the morphology of failure area and determine the root cause of failure. Results of the failure analysis provides a basis for improving manufacturing process and device reliability.