Vertical Channel Thin Film Transistors Research Articles

Scaling Benefits for Active and Gate Insulator of Vertical Channel Thin-Film Transistors Using Atomic Layer Deposited InGaZnO Channel

Scaling Benefits for Active and Gate Insulator of Vertical Channel Thin-Film Transistors Using Atomic Layer Deposited InGaZnO Channel

Research Progress of Vertical Channel Thin Film Transistor Device.

Thin film transistors (TFTs) as the core devices for displays, are widely used in various fields including ultra-high-resolution displays, flexible displays, wearable electronic skins and memory devices, especially in terms of sensors. TFTs have now started to move towards miniaturization. Similarly to MOSFETs problem, traditional planar structure TFTs have difficulty in reducing the channel's length sub-1μm under the existing photolithography technology. Vertical channel thin film transistors (V-TFTs) are proposed. It is an effective solution to overcome the miniaturization limit of traditional planar TFTs. So, we summarize the different aspects of VTFTs. Firstly, this paper introduces the structure types, key parameters, and the impact of different preparation methods in devices of V-TFTs. Secondly, an overview of the research progress of V-TFTs' active layer materials in recent years, the characteristics of V-TFTs and their application in examples has proved the enormous application potential of V-TFT in sensing. Finally, in addition to the advantages of V-TFTs, the current technical challenge and their potential solutions are put forward, and the future development trend of this new structure of V-TFTs is proposed.

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In–Ga–Zn–O bilayer channel configuration

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs. Here we show a novel strategy to introduce an In–Ga–Zn–O (IGZO) bilayer channel configuration, which was prepared by atomic-layer deposition (ALD), in terms of structural and electrical passivation against the back-channel effects. Two-dimensional electron gas was effectively employed for improving the operational reliability of the VTFTs by inducing strong confinement of conduction electrons at heterojunction interfaces. The IGZO bilayer channel structure was composed of 3 nm-thick In-rich prompt (In/Ga = 4.1) and 12 nm-thick prime (In/Ga = 0.7) layers. The VTFTs using bilayer IGZO channel showed high on/off ratio (4.8 × 109), low SS value (180 mV dec−1), and high current drivability (13.6 μA μm−1). Interestingly, the strategic employment of bilayer channel configurations has secured excellent device operational stability representing the immunity against the bias-dependent hysteretic drain current and the threshold voltage instability of the fabricated VTFTs. Moreover, the threshold voltage shifts of the VTFTs could be suppressed from +5.3 to +2.6 V under a gate bias stress of +3 MV cm−1 for 104 s at 60 °C, when the single layer channel was replaced with the bilayer channel. As a result, ALD IGZO bilayer configuration could be suggested as a useful strategy to improve the device characteristics and operational reliability of VTFTs.

Device Characterization of Nanoscale Vertical-Channel Transistors Implemented with a Mesa-Shaped SiO2 Spacer and an In–Ga–Zn–O Active Channel

A nanoscale vertical-channel thin film transistor (V-TFT) with a channel length shorter than 160 nm was fabricated and characterized, in which In–Ga–Zn–O (IGZO) and SiO2 thin films were prepared by atomic layer deposition and plasma-enhanced chemical-vapor deposition as active and spacer layers, respectively. The prototype device showed sound transistor operation with an on/off ratio of 8.8 × 103 and robust stabilities without any shift in transfer curves under positive/negative bias stresses at 1 MV/cm for 104 s. It was also noteworthy that there was no anomalous increase in off-state current during the positive bias stress test, which is suggested to originate from a high-quality interface between the SiO2 spacer and IGZO active layers on the back-channel region. Alternatively, high off-state current levels were found to result from the formation of conduction paths generated by carbon-related residues on the vertical back-channel region through the surface time-of-flight secondary ion mass spectrometer analysis. Improvements in device performance and analysis of operation failures will provide insight into the implementation of nanoscale oxide V-TFTs.

Implementation of oxide vertical channel TFTs with sub-150 nm channel length using atomic-layer deposited IGZO active and HfO2 gate insulator

We fabricated vertical channel thin film transistors (VTFTs) with a channel length of 130 nm using an ALD In–Ga–Zn–O (IGZO) active channel and high-k HfO2 gate insulator layers. Solution-processed SiO2 thin film, which exhibited an etch selectivity as high as 4.2 to drain electrode of indium-tin oxide, was introduced as a spacer material. For the formation of near-vertical sidewalls of the spacer patterns, the drain and spacer were successively patterned by means of two-step plasma etching technique using Ar/Cl2 and Ar/CF4 etch gas species, respectively. The SiO2 spacer showed smooth surface morphology (R q = 0.45 nm) and low leakage current component of 10–6 A cm−2 at 1 MV cm−1, which were suggested to be appropriate for working as spacer and back-channel. The fabricated VTFT showed sound transfer characteristics and negligible shifts in threshold voltage against the bias stresses of +5 and −5 V for 104 s, even though there was abnormal increase in off-currents under the positive-bias stress due to the interactions between hydrogen-related defects and carriers. Despite the technical limitations of patterning process, our fabricated prototype IGZO VTFTs showed good operation stability even with an ultra-short channel length of 130 nm, demonstrating the potential of ALD IGZO thin film as an alternative channel for highly-scaled electronic devices.

High-Performance Thin-Film Transistors of Quaternary Indium-Zinc-Tin Oxide Films Grown by Atomic Layer Deposition.

A new deposition technique is required to grow the active oxide semiconductor layer for emerging oxide electronics beyond the conventional sputtering technique. Atomic layer deposition (ALD) has the benefits of versatile composition control, low defect density in films, and conformal growth over a complex structure, which can hardly be obtained with sputtering. This study demonstrates the feasibility of growing amorphous In-Zn-Sn-O (a-IZTO) through ALD for oxide thin-film transistor (TFT) applications. In the ALD of the a-IZTO film, the growth behavior indicates that there exists a growth correlation between the precursor molecules and the film surface where the ALD reaction occurs. This provides a detailed understanding of the ALD process that is required for precise composition control. The a-IZTO film with In/Zn/Sn = 10:70:20 was chosen for high-performance TFTs, among other compositions, regarding the field-effect mobility (μFE), turn-on voltage ( Von), and subthreshold swing (SS) voltage. The optimized TFT device with the a-IZTO film thickness of 8 nm revealed a high performance with a μFE of 22 cm2 V-1 s-1, Von of 0.8 V, and SS of 0.15 V dec-1 after annealing at 400 °C for 30 min. Furthermore, an emerging device such as a vertical channel TFT was demonstrated. Thus, the a-IZTO ALD process could offer promising opportunities for a variety of emerging oxide electronics beyond planar TFTs.

Flexible vertical-channel thin-film transistors using In-Ga-Zn-O active channel and polyimide spacer on poly(ethylene naphthalate) substrate

A flexible vertical-channel thin-film transistor (VTFT) with a channel length of 400 nm was fabricated on a poly(ethylene naphthalate) substrate. The vertical gate-stack composed of gate electrode/gate insulator/active channel was prepared by a conformal atomic layer deposition and a dry etching process of an organic polyimide spacer. The transfer characteristics of the fabricated flexible VTFT were well confirmed after the postannealing process at 200 °C, in which the on/off ratio was obtained to be 1.8 × 102. The threshold voltage shifts were estimated to be +6.1 and −4.5 V under the positive and negative bias-stress conditions for 104 s, respectively. The device characteristics showed no remarkable degradation when delaminating from the carrier glass substrate. Furthermore, there were no marked changes in transfer curves even when the device was bent with a radius of curvature of 10 mm. A suitable choice of spacer material, optimization of the dry etching process, and employment of ultra-thin flexible film substrate were suggested to appropriate solutions for enhancing the device performance of the proposed flexible VTFTs.

1.1: Invited Paper: TFT Backplane for Display

Thin Film Transistors (TFT) are being widely used as backplane to drive display components, such as LCD, OLED, and even u‐LCD. A‐Si, poly Si, oxide, and organic are common materials for TFT. Mobility, scale‐up and long term stability are among the key concern for TFT. Vertical channel thin film transistors (VTFTs) are proposed as an effective approach to reduce driving voltage and power consumption for achieving high speed and high resolution displays. Considering that oxide semiconductors have large‐area compatible processes, it will be better to find a method for achieving low driving voltages with conventional optical lithography machines used for large area display panels. In this talk, we will review the state of art of the vertical TFTs and explore the major fabrication issues. In addition, we will examine amorphous indium gallium zinc oxide (a‐IGZO) vertical channel TFT fabricated at low temperature to evaluate the impact of gate dielectric on electric characteristics of the vertical vis‐à‐vis planar TFTs. VTFTs employing vertical amorphous a‐IGZO channel of 500 nm have been fabricated without additional photolithography process. The various issues related to the improved device performance will be addressed. Solution based organic TFT will also be examined to explore its feasibility for backplane to drive display and other components.

Improvement in Device Performance of Vertical Thin-Film Transistors Using Atomic Layer Deposited IGZO Channel and Polyimide Spacer

Technical strategies for improving the device characteristics of the In–Ga–Zn-O (IGZO) vertical channel thin-film transistors (VTFTs) were presented and investigated. The vertical sidewall was constructed by dry-etch process and subsequently covered with IGZO, Al2O3, and AZO as active, gate insulator, and gate electrode layers by means of conformal atomic-layer-deposition. An abrupt profile and flat back-channel were achieved by employing the spin-coated polyimide (PI) spacer. The Off-current was additionally alleviated simply by cutting the area of an active layer. The fabricated IGZO VTFT using PI spacer with an “active-cut” structure exhibited an On/off ratio of $10^{3}$ , a linear mobility of 7.1 cm2/Vs, and a subthreshold swing of 1.2 V/decade.

(Invited) Vertical Channel Amorphous Indium Gallium Zinc Oxide Thin Film Transistors

Vertical channel thin film transistors (VTFTs) are proposed as an effective approach to reduce driving voltage and power consumption for achieving high speed and high resolution displays. VTFTs with amorphous silicon (a-Si) technology have severe problems related to low on/off current ratio (Ion/off), high drain-leakage current, and absence of saturation behavior at high drain voltages. In this concern, thin gate insulator plays a key role to result well behaved a-Si VTFT characteristics such as clear saturation behavior at high drain voltage, low leakage current and good device performance with high Ion/off. However, poor mobility and contact resistance due to space charge limited current a-Si VTFT become increasingly noticeable, when the channel length is scaled down to nanometer dimensions. In contrast, the oxide semiconductor can be scaled to a very short channel without deteriorating the device performances. Considering that oxide semiconductors have large-area compatible processes, it will be better to find a method for achieving low driving voltages with conventional optical lithography machines used for large area display panels. In this talk, we will review the state of art of the vertical TFTs and explore the major fabrication issues. In addition, we will examine amorphous indium gallium zinc oxide (a-IGZO) vertical channel TFT fabricated at low temperature to evaluate the impact of gate dielectric on electric characteristics of the vertical vis-à-vis planar TFTs. VTFTs employing vertical amorphous a-IGZO channel of 500 nm have been fabricated without additional photolithography process. The various issues related to the improved device performance will be addressed. Figure 1

Vertical Oxide Thin-Film Transistor with Solution-Processed Channel Define Layer

High performance thin-film transistor (TFT) is essential for the next-generation display. Especially, scale-downed TFT becomes very important to develop high resolution display. The vertical-channel TFTs (V-TFTs) attracts lots of interests from the view point of minimizing pixel size because V-TFTs have very small footprint compared to the lateral TFT. V-TFTs provide the smallest pixel size without the limitation of channel length. [1] In addition, V-TFTs could show high strain stress stability due to the small channel size formed vertically when they are adapted in flexible display. Channel length of V-TFTs is controlled by the thickness of spacer placed between source and drain. Since the main purpose of adoption of V-TFTs is to increase the current driving ability, typical channel length of V-TFT is shorter than 1 um (~0.5 um). The length of channel in vertical TFT, however, should be adjustable according to the TFT applications. The major method to deposit spacer which determine the channel length (channel define layer) is vacuum process such as plasma-enhanced chemical vapor deposition (PECVD). Such vacuum process could provide high film performance, quality and good uniformity. Nonetheless, vacuum process has disadvantage in the deposition of spacer with thick thickness because of very long process time. In contrast, solution-process coating is easy and fast method. By controlling coating speed and time, solution process provides thick films uniformly. Furthermore, solution process can be applied using both of organic and inorganic materials. While inorganic materials result in films with low defects, the space processed with organic materials yields low stress, making this suitable for the flexible vertical TFTs. In this study, we fabricate vertical TFT with spacers deposited with various materials such as organic and inorganic by solution-process coating. We also investigate back-channel effect and TFT strain stress depending on the kinds of spacer materials. We select three different types of materials for the spacer; SiO2, PI, carbon based organic material. Solution-processed SiO2 film have dielectric constant of 4.27 and similar film quality with PECVD SiO2. The solution-processed films show very low leakage current of 1.35x10-9A/cm-2at 0.1MV/cm. Carbon based organic material also has low dielectric constant and is approximately 1um~3um thick. We studied the effect of back-channel according to various spacer materials. Instead of V-TFTs, top gate staggered TFTs were fabricated to mimic the structure of V-TFT because both TFTs have same process sequence. Figure 1(a) shows the schematic structure of top-gate TFT. The various buffer layers corresponding to the spacer in V-TFT were deposited by solution processes. The TFT with solution-processed film did not show degradation of electrical characteristics in comparison to that with PECVD SiO2. After confirming the feasibility of solution-processed spacer for the vertical TFT, three types of solution-processed layer are applied to actual vertical TFT as a spacer. The patterned source ITO electrode was coated with solution processed spacer, followed by the deposition of drain electrode. Drain and spacer were patterned with spacer mask. In sequence, active, gate insulator and gate are deposited and patterned at once. We will report the performance of V-TFTs with solution processed spacer in terms of mobility, stability, and thermal stability. Figure 1. (a) Schematic diagram of top-gate TFT, (b) Schematic structure of vertical TFT with solution processed spacer Acknowledgements This work was supported by 'The Cross-Ministry Giga KOREA Project' grant from the Ministry of Science, ICT and Future Planning, Korea [GK15D0100].

Vertical Conduction in the New Field Effect Transistors: p-Type and n-Type Vertical Channel Thin Film Transistors

In order to pursue the integration, the research activities were oriented during the last years towards channel conduction in a plan perpendicular to the substrate surface while in the traditional architectures the conduction is parallel to the surface, under the gate. In the integrated technologies, this approach led to the FinFET. But in this case, even though the conduction plan is perpendicular to the substrate surface, the direction of the drain currents remains parallel to the substrate. New electronics devices were designed with the channels vertically oriented. In the monolithic technologies, many drawbacks have stopped this trend. However, in the case of thin film technologies, the approach appeared more suitable. The channel conduction is thus vertically oriented. But a drawback comes from the leakage current flowing between source and drain. The introduction of an insulating barrier in-between and the decrease of the thickness of the channel active layer, led to electrical behavior much more suitable for applications. After an overview of the different approaches developed as well in monolithic technologies as in thin film technologies, this presentation will give details on the concept and on the fabrication process of quasi-vertical thin film transistors. The associated electrical results will be described, analyzed and commented.

(Invited) Towards Higher Integration Thin Film Technology by Involving P-Type and N-Type Vertical Channel Thin Film Transistors

The silicon based thin film transistors (TFTs) technological process evolution is governed by electrical performance improvements that are needed for the numerous fields of large area electronic applications. The TFTs must be fabricated at a temperature low enough to be compatible with the substrates. In addition, one of the challenges is to increase the equivalent electrical current density per substrate area in order to increase the circuit integration. Similarly to ICs technologies, the improvement passes through a three dimensional approach that involves a new geometry with the channels perpendicular to the substrate surface. But also similarly to ICs, a drawback comes from the leakage current flowing between source and drain. The introduction of an insulating barrier between stacked source and drain regions and the decrease of the thickness of the quasi-vertical channel active layer, lead to electrical behavior of p-type and n-type thin film transistors much more suitable for applications.

(Invited) Vertical Channel Thin Film Transistor: Improvement Approach Similar to Multigate Monolithic CMOS Technology

The silicon based thin film transistors (TFTs) technology evolution is governed by electrical performances that are needed for many applications. Previous papers highlighted the influence of the process, the quality and the nature of the channel material on their electrical properties. TFTs had as well channel parallel to the substrate surface as quasi-vertical channels. This last choice allows an increase of the equivalent current density flowing in the circuit thanks to a shorter channel length and a higher channel width, for the same lithographical node. However, the drain-source leakage current was measured proportional to the source-drain face-to-face area, while Ion is proportional to channel width. This behavior was also observed in vertical monolithic structures. To minimize this effect two main ways are proposed: decreasing the scale, or including a physical barrier between source and drain. We will see that these approaches are really similar to ULSI technology ones.

Vertical Channel Thin Film Transistor Technology: Similar Approach with 3D-ULSI Monolithic Technology

The previous thin film transistor studies involved planar process that means channel parallel to the substrate surface. Another way passes by a modification of the spatial geometry, more especially by the creation of vertical channels. This allows an increase of the equivalent current density flowing in the circuit thanks to two major modifications, the channel length that can be much shorter and the channel width that can be much higher, for the same design rules and for the same substrate area. The approach is thus similar to the recent evolution of the monolithic silicon technology. After the presentation of the interest of such vertical channel ways on both ULSI and thin film technologies, results on vertical TFTs are presented and discussed. We finally give comments on the common approaches between nano- and giga-electronics involving three dimensional geometry, in order to show that their basic scientific principles are roughly the same.