(Invited) Vertical Channel Amorphous Indium Gallium Zinc Oxide Thin Film Transistors

Abstract

Vertical channel thin film transistors (VTFTs) are proposed as an effective approach to reduce driving voltage and power consumption for achieving high speed and high resolution displays. VTFTs with amorphous silicon (a-Si) technology have severe problems related to low on/off current ratio (Ion/off), high drain-leakage current, and absence of saturation behavior at high drain voltages. In this concern, thin gate insulator plays a key role to result well behaved a-Si VTFT characteristics such as clear saturation behavior at high drain voltage, low leakage current and good device performance with high Ion/off. However, poor mobility and contact resistance due to space charge limited current a-Si VTFT become increasingly noticeable, when the channel length is scaled down to nanometer dimensions. In contrast, the oxide semiconductor can be scaled to a very short channel without deteriorating the device performances. Considering that oxide semiconductors have large-area compatible processes, it will be better to find a method for achieving low driving voltages with conventional optical lithography machines used for large area display panels. In this talk, we will review the state of art of the vertical TFTs and explore the major fabrication issues. In addition, we will examine amorphous indium gallium zinc oxide (a-IGZO) vertical channel TFT fabricated at low temperature to evaluate the impact of gate dielectric on electric characteristics of the vertical vis-à-vis planar TFTs. VTFTs employing vertical amorphous a-IGZO channel of 500 nm have been fabricated without additional photolithography process. The various issues related to the improved device performance will be addressed. Figure 1