(Invited) Towards Higher Integration Thin Film Technology by Involving P-Type and N-Type Vertical Channel Thin Film Transistors

Abstract

The silicon based thin film transistors (TFTs) technological process evolution is governed by electrical performance improvements that are needed for the numerous fields of large area electronic applications. The TFTs must be fabricated at a temperature low enough to be compatible with the substrates. In addition, one of the challenges is to increase the equivalent electrical current density per substrate area in order to increase the circuit integration. Similarly to ICs technologies, the improvement passes through a three dimensional approach that involves a new geometry with the channels perpendicular to the substrate surface. But also similarly to ICs, a drawback comes from the leakage current flowing between source and drain. The introduction of an insulating barrier between stacked source and drain regions and the decrease of the thickness of the quasi-vertical channel active layer, lead to electrical behavior of p-type and n-type thin film transistors much more suitable for applications.