Variation Of Electrical Characteristics Research Articles

A 6T1C pixel circuit compensating for TFT electrical characteristics variations, voltage drop, and OLED degradation

A voltage-programmed pixel circuit based on low-temperature poly-silicon (LTPS) thin-film transistors (TFTs) is presented for active-matrix organic light-emitting diode (AMOLED) displays. The circuit consists of six p-type transistors and one capacitor (6T1C). During the extraction stage, the circuit extracts the driving TFT’s threshold voltage and the power supply voltage. During the data input stage, the circuit generates a charging voltage, which is associated with the driving TFT’s mobility and the OLED’s threshold voltage. Consequently, the pixel circuit, using only one capacitor, compensates not only for the TFT’s electrical characteristics variations, i.e., the threshold voltage variation and mobility variation, but also for the power supply voltage drop and the OLED degradation. The circuit simulation results reveal that the OLED current error rates (CERs) are lower than 5.09% when the threshold voltage varies by ±0.5V, lower than 3.61% when the mobility varies by ±30%, and lower than 9.16% when the voltage drop varies by −0.5V in the data voltage range.

Structural and electrical characteristics of double perovskite: Nd2CoMnO6

The double perovskite material, Nd2CoMnO6, was prepared by a standard mixed oxide route. We found the monoclinic structure of the studied material from X-ray diffraction data analysis. The microstructure study shows that the presence of almost uniform distribution of grains with small voids. The analysis of both temperature and frequency variation of electrical and dielectric characteristics have been discussed. The frequency dependence of dielectric parameter was explained as per the Maxwell-Wagner model. An anomaly behaviour was observed in the temperature dependence dielectric curve corresponds to the ferroelectric-paraelectric phase transition. We found the presence of both grain and grain boundary effects in the complex impedance analysis. The occurrence of the negative temperature coefficient of resistance (NTCR) behaviour indicates this material is a semiconducting type of material. From the analysis of J-E characteristics curve, we found the low low-leakage current density. The scaling nature of Z″ and M″ specifies that the relaxation phenomena are almost independent of temperature. The existing property makes more appropriate for modern electronic device.

High‐Performance Flexible MoS2 Transistors Using Au/Cr/Al/Au as Source/Drain Electrodes

Abstract2D transition metal dichalcogenides such as molybdenum disulfide (MoS2) are promising candidates for flexible electronics because of their bandgap tunability, high carrier mobility, and mechanical flexibility. However, flexible MoS2 field effect transistors (FETs) are typically faced with high contact resistance which is identified as a critical limiting factor to their potential applications. The present work successfully addresses this challenge by using Al contacts without any annealing process. It is found that the contact resistance is strongly coupled to the Al thickness, increasing the Al thickness is beneficial to reduce the contact resistance. The observed variation in the device electrical characteristics can be associated with the formation of the natural aluminum oxide (AlxOy) film at the interface. An ultrathin Au insert layer can further advance the device performance. An optimal contact resistance of 2.03 kΩ and an on/off current ratio of 1.57 × 109 can be achieved in the flexible MoS2 FETs using Au/Cr/Al/Au as source/drain electrodes. Furthermore, no apparent degradation in the device properties is observed under systematic cyclic bending testing with bending radii of 18 and 15 mm. The successful integration of Au/Cr/Al/Au source/drain electrodes into MoS2 FETs promises its potential application in flexible electronic devices.

Modeling the electrical degradation of AlGaN-based UV-C LEDs by combined deep-level optical spectroscopy and TCAD simulations

The long-term stability of ultraviolet (UV)-C light-emitting diodes (LEDs) is of major importance for many applications. To improve the understanding in this field, we analyzed the degradation of AlGaN-based UVC LEDs and modeled the variation of electrical characteristics by 2D simulations based on the results of deep-level optical spectroscopy (DLOS). The increase in the forward leakage current observed during ageing was ascribed an increase in trap-assisted tunneling. The analysis of the degradation kinetics suggests the role of a defect diffusion process, possibly involving impurities coming from the p-type layers.

A Pixel Circuit for Compensating Electrical Characteristics Variation and OLED Degradation

In recent years, the active-matrix organic light-emitting diode (AMOLED) displays have been greatly required. A voltage compensation pixel circuit based on an amorphous indium gallium zinc oxide thin-film transistor is presented for AMOLED displays. The circuit is composed of five transistors–two capacitors (5T2C) in combination with an OLED. In the circuit, the threshold voltages of both the transistor and the OLED are extracted simultaneously in the threshold voltage extraction stage, and the mobility-related discharge voltage is generated in the data input stage. The circuit not only can compensate the electrical characteristics variation, i.e., the threshold voltage variation and mobility variation, but also can compensate the OLED degradation. Furthermore, the circuit can prevent the OLED flicker, and can achieve the wide data voltage range. The circuit simulation results show that the OLED current error rates (CERs) are lower than 3.89% when the transistor’s threshold voltage variation is ±0.5V, lower than 3.49% when the mobility variation is ±30%.

Applying of C8-BTBT-Based EGOFETs at Different pH Values of the Electrolyte

Electrolyte-gated organic field-effect transistors (EGOFETs) is a popular platform for numerous sensing and biosensing applications in aqueous media. In this work, the variation of electrical characteristics of EGOFETs based on small-molecule organic semiconductor C8-BTBT and polystyrene blend in water solutions at different pH values was investigated. A positive shift of the threshold voltage with near-Nernstian pH sensitivity was demonstrated in the pH range from 4.9 to 2.8, while no measurable pH dependence in the range from 4.9 to 8.6 pH was registered. These results indicate chemical doping of the molecules of organic semiconductors by protons from the electrolyte in the acidic region. In order to check the applicability of the EGOFETs in a flow mode, a flow chamber was designed and assembled. The preliminary results obtained in the flow mode measurements showed a fast response to pH variation.

Variation of electrical and dielectric characteristics of Schottky diodes (SDs) depending on the existence of PVC and carbon-nanotube (CNT)-doped PVC interlayers

Variation of electrical and dielectric characteristics of Schottky diodes (SDs) depending on the existence of PVC and carbon-nanotube (CNT)-doped PVC interlayers

Neutrosophic Fuzzy Neural Network Modelling and Current-Voltage Analysis for Forecasting Post-Surgery Risks

The electrical reaction of bioactive sites in the individual’s body can be used to diagnose various disorders. Forecasts are made by examining the electric signal of the biologically active points onto patients. Measurements of the organ’s present level and variations in the passive electrical characteristics at specific bioactive sites on the body were made to evaluate the influence on the organ. The study aims to create a Neutrosophic fuzzy neural network (NFNN) approach to forecast the probability of complications following surgery. The research investigates a neural network method for predicting hazards associated with post-surgical care. Examining the current-voltage features of the biologically active spots forms the basis for the characteristics of the risk classifiers. By looking at patients who had been given a diagnosis of a disease, the training, as well as verification samples, as well as verification samples were created. Patients with type 1 had successful operations, but type 2 patients experienced a variety of post-operative problems, and type 3 patients needed extra treatment. The created classifiers show an excellent ability to foresee severe circumstances during surgical therapy. The neutrosophic fuzzy neural network model may be more sophisticated and advanced compared to conventional fuzzy neural network models. It can help differentiate the proposed model from existing models and highlight its unique features and advantages. The results show that the proposed

Application of long short-term memory modeling technique to predict process variation effects of stacked gate-all-around Si nanosheet complementary-field effect transistors

Emerging machine-learning (ML) methodology has been overcoming the challenging task of analyzing the process variation effect of nanoscale devices using 3-D stochastic device simulation. In this study, the effects of process variations on the electrical characteristics of the stacked gate all around (GAA) silicon nanosheet (NS) complementary field effect transistors (CFETs) are predicted using long short-term memory (LSTM) based ML model. The LSTM algorithm is less time-consuming and computationally effective as compared to conventional device modeling tools. For this work, a two-channel stacked CFET, formed by folding n-FET on top of p-FET, is considered. We utilize six important process parameters as input features to the LSTM model and estimate the variations in key electrical characteristics, such as threshold voltage (VTH), off-current (IOFF), on-current (ION), subthreshold slope (SS), and drain induced barrier lowering (DIBL). To avoid overfitting in the training phase, an early stopping regularization technique is applied to construct a high-performance LSTM model. In addition, to compare the predictive performance of our proposed ML-based LSTM model, the baseline MLP (multi-layer perceptrons) model is implemented. The results of this study show that the LSTM model with an r2-score > 95% outperforms the baseline model which has r2-score < 75%. Furthermore, the estimated rmse of LSTM in an order of 10−7 is 10 times lower than that of the baseline model whose rmse is in an order of 10−6.

Growth Dynamics of SnSe Thin Films on Annealing of Precursor Layers Stacked by Multisource Sequential Elemental Layer Deposition

SnSe thin films were grown using multisource sequential elemental layer deposition (MSELD) technique on annealing of Sn/Se stacked precursor layers. Annealing allows interlayer diffusion of ‘Se’ atoms into ‘Sn’ lattice and, thus, leads to enhanced grain growth in the form of SnSe nanocrystals. The change in annealing temperature influenced the interlayer growth dynamics of stacked precursor layers which leads to varied Sn, SnO, SnSe alloy phase formation. These changes in the alloy formation bring about variations in composition, structure, morphology, optical and electrical characteristics of the films. Also, the present investigation exhibits better solar characteristics of thin films prepared using MSELD over the existing PV technologies.

Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors

Abstract3D NAND has been enabling continuous NAND density and cost scaling beyond conventional 2D NAND since sub‐20‐nm nodes. However, its poly‐Si channel suffers from low mobility, instability caused by grain boundaries, and large device‐to‐device variations in electrical characteristics at highly scaled device dimensions. These drawbacks can be overcome by introducing an amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) channel, which has the advantages of ultralow OFF current, back‐end‐of‐line compatibility, higher mobility than poly‐Si, and free of grain boundaries due to the amorphous nature. In this work, ultrascaled floating‐gate (FG) transistors with a channel length down to 60 nm are reported, achieving the highest ON current of 127 µA µm−1 among all reported a‐IGZO‐based flash devices for high‐density, low‐power, and high‐performance 3D NAND applications. Furthermore, a nonvolatile and area‐efficient ternary content‐addressable memory (TCAM) with only two parallel‐connected a‐IGZO FG transistors is experimentally demonstrated to address the TCAM scalability issue. Experimentally calibrated array‐level simulations show that this design achieves at least a 240 × array‐size scalability and a 2.7‐fold reduction in search energy than TCAMs based on complementary metal‐oxide‐semiconductor technology using 16 transistors, two‐transistor‐two‐resistive random access memory, and two‐ferroelectric field‐effect‐transistor.

Degradation assessment of 1.2-kV SiC MOSFETs and comparative study with 1.2-kV Si IGBTs under power cycling

Although SiC MOSFETs has better performance than Si IGBTs, some obvious differences between SiC materials and devices and Si equivalents affect the robustness and reliability of SiC MOSFETs. In this paper, an in-depth comparison of degradation assessment of 1.2-kV SiC MOSFETs and 1.2-kV Si IGBTs under the same power cycling test condition is presented. The variations of electrical and thermal characteristics of the two kinds of devices are investigated comparatively. Both devices chip-related and package-related degradation analysis is provided to explain each parameter variation. And a detailed physical analysis is conducted to have a better understanding of the root cause of the aging. From test results, SiC MOSFETs with the same package process will fail earlier than Si IGBTs. After a long period of PCT, Si IGBTs are not observed other failure modes except for solder layer degradation, but SiC MOSFETs are successively observed three failure modes: solder layer crack and delamination, bond crack, threshold voltage shift. However, chip-level degradation failures are much later than package-level degradation failures for SiC MOSFETs. It is shown that although chips still have unresolved reliability problems for SiC MOSFETs, the package reliability is the shortcoming that limits their long-term service life.

Adjunctive Diagnostic Methods for Skin Cancer Detection: A Review of Electrical Impedance-Based Techniques.

Skin cancer is among the fastest-growing cancers with an excellent prognosis, if detected early. However, the current method of diagnosis by visual inspection has several disadvantages such as overlapping tumor characteristics, subjectivity, low sensitivity, and specificity. Hence, several adjunctive diagnostic techniques such as thermal imaging, optical imaging, ultrasonography, tape stripping methods, and electrical impedance imaging are employed along with visual inspection to improve the diagnosis. Electrical impedance-based skin cancer detection depends upon the variations in electrical impedance characteristics of the transformed cells. The information provided by this technique is fundamentally different from other adjunctive techniques and thus has good prospects. Depending on the stage, type, and location of skin cancer, various impedance-based devices have been developed. These devices when used as an adjunct to visual methods have increased the sensitivity and specificity of skin cancer detection up to 100% and 87%, respectively, thus demonstrating their potential to minimize unnecessary biopsies. In this review, the authors track the advancements and progress made in this technique for the detection of skin cancer, focusing mainly on the advantages and limitations in the clinical setting. © 2022 Bioelectromagnetics Society.

Enhancement of thermoelectric properties of low-toxic and earth-abundant copper selenide thermoelectric material by microwave annealing

Our current work aims to enhance the thermoelectric properties of p-type copper selenide (Cu2Se), a low toxic, earth-abundant intermediate material for thermoelectric applications by a low-cost, simple and fast microwave-assisted metallurgy route. Hot pressed copper selenide pellets were treated at various temperatures in the range of 250 oC to 425 oC in a microwave furnace. We analyze the variation of several characteristics of the samples, such as electrical, thermal, structural, microscopic, dielectric, and mechanical properties, when the samples are exposed to different annealing conditions. Broadband dielectric spectroscopy (BDS) analysis facilitated the comprehensive study of variation of AC electrical characteristics of the samples such as AC conductivity, dielectric permittivity storage, dielectric loss, and AC capacitance, with temperature and frequency. The results indicate exceptional electrical, thermal, and mechanical properties for samples annealed at 375 oC with high room temperature electrical conductivity of 538.3 S/cm and ultra-low thermal conductivity of 0.59 W/mK. The crystallinity improved as the annealing temperature increased, as did the formation of oxides over 400 oC. The samples have a high strength with maximum nanohardnesss and compression strength of 3.75 GPa and 326.75 MPa, respectively that has been a significant improvement over the existing studies on copper selenides.

Numerical and experimental investigation for analyzing the temperature influence on the performance of photovoltaic module

&lt;abstract&gt; &lt;p&gt;The effect of temperature is considered a significant factor in controlling the output voltage of the photovoltaic (PV) module. In this work, a numerical analysis with an experimental demonstration were investigated to analyze the temperature effect on the performance of PV module. In the numerical part, the current-voltage I-V and power-voltage P-V curves of the PV module were simulated under the influence of various module temperature ranged from 25 to 65 ℃ as well as various solar radiation from 200 to 1000 W/m&lt;sup&gt;2&lt;/sup&gt;. In addition, the variation of PV output electrical characteristics with a module temperature were performed to analyze the temperature coefficients of the PV module. Moreover, the experimental demonstration was performed to analyze performance of the PV module under the real weather conditions of Iraq. The numerical results conclude that the maximum power was recorded 165 W at 1000 W/m&lt;sup&gt;2&lt;/sup&gt; solar irradiance and 25 ℃ PV module temperature. Furthermore, the temperature coefficient was recorded a maximum value with output power about (−0.26) %/℃. Besides, the experimental results show that the maximum power was recorded 131.2 W at solar irradiance about 920 W/m&lt;sup&gt;2&lt;/sup&gt;.&lt;/p&gt; &lt;/abstract&gt;

Gold nanoparticle decorated graphene for efficient sensing of NO2 gas

We have devised a method to simultaneously reduce graphene oxide and gold metal ions onto the surface of graphene. The nanohybrid was in-turn used for efficient sensing of NO2 gas. The nanohybrid was characterized using X-ray diffractometry, field emission scanning electron microscopy (FESEM), UV–Visible spectroscopy and Raman spectroscopy. Morphological details revealed the successful growth of gold nanoparticles onto graphene sheets. Considerable variations in electrical characteristics of graphene-Au nanohybrid were recorded upon the exposure of NO2 gas. The sensor showed fast response and recovery time and good response of 3.2 % for 50 ​ppm NO2 gas. The method can pave the way to develop miniaturized gas sensors useful for environmental monitoring.

Electrical Performance Enhanced Doping Less Tunnel Field Effect Transistor by Metal Electrode Work Function Engineering

Tunnel field effect transistor (TFET) has been proposed as one of the promising alternative devices to MOSFET since it has low power consumption and excellent subthreshold swing (SS) characteristics of less than 60 mV / dec. However, conventional TFET fabrication requires ion implantation process to form p-i-n structure in active region, which induces a random distribution of dopant atoms. In the nm-scale device, even a small number of dopant atom dispersion can cause electrical characteristic variations such as threshold voltage (Vt)1, so alternative method for forming p-i-n region instead of doping process is needed.Doping-less TFET (DL-TFET) introduces charge plasma concept2 that controls carrier concentration of Si region by band alignment in MOS contact not by doping process, so random dopant fluctuation (RDF) issue can be solved. Since the active region carrier concentration is determined by the work function of the metal electrode, it is necessary to analyze the device performance by the metal work function condition. In this work, we manufactured doping-less TFET with adapting various metal work function to enhance electrical performance, and conducted CV measurement in MOS structure to confirm Si band bending and charge plasma by analyzing flat band voltage (VFB).DL-TFET was fabricated on SOI wafer and the overall structure is shown in Fig. 1. (a). In the case of the source region, the metal work function must be larger than that of Si to form the p-type active area, and drain region, on the contrary, must have smaller work function for n-type active region. Obviously, gate electrode work function has similar work function to intrinsic Si. For fabricating DL-TFET, we conducted reactive ion etch (RIE) process to define Si active layer and formed gate oxide (SiO2) by thermal oxidation. Then, we deposited gate metal and removed source / drain region oxide for contact hole. Spacer oxide was deposited using PECVD to isolate each metal electrode, finally we deposited source / drain metal. IV characteristics are shown in Fig. 1. (b), (c) when Pt / W / Al is applied at source / gate / drain area and we compared IV curve of various metal electrode and thermal conditions.In addition, to confirm whether the charge plasma was formed as intended, we fabricated MOS capacitor with 10 nm oxide thickness as shown in Fig. 1. (d). Through frequency sweep, we determined suitable bias frequency and conducted CV measurement (see Fig. 1. (e), (f), (g)). Band bending and charge plasma were confirmed by evaluating VFB shift depending on work function of each MOS gate material (see Fig. 1. (h)). Finally, we discussed the optimal metal electrode combination in terms of ambipolar current, off current, on current and SS. Key Words: Charge plasma, Doping-less TFET, Work function, CV measurement References Changho Shin, Jeong-Kyu Kim, Gwang-Sik Kim, Hyunjae Lee, Changhwan Shin, Jong-Kook Kim, Byung Jin Cho, and Hyun-Yong Yu, “Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal–Interlayer–Semiconductor Source/Drain,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, No. 11, pp 4167-4172, Nov 2016. doi: 10.1109/TED.2016.2606511 Raymond J. E. Hueting, Bijoy Rajasekharan, Cora Salm, and d Jurriaan Schmitz, " The Charge Plasma P-N Diode" IEEE ELECTRON DEVICE LETTERS, vol. 29, issue 12, pp 1367-1369, Dec 2008. doi: 10.1109/LED.2008.2006864 Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2021, the MOTIE (Ministry of Trade, Industry & Energy 20010836) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

Electrical Coupling for Monolithic 3-D Integrated Circuit Consisting of Feedback Field-Effect Transistors

In this study, for two cases of monolithic 3-dimensional integrated circuit (M3DIC) consisting of vertically stacked feedback field-effect transistors (FBFETs), the variation of electrical characteristics of the FBFET was presented in terms of electrical coupling by using technology computer aided design (TCAD) simulation. In the Case 1, the M3DIC was composed with an N-type FBFET in an upper tier (tier2) and a P-type FBFET in a lower tier (tier1), and in the Case 2, it was composed with the FBFETs of opposite type of the Case 1 on each tier. To utilize the FBFET as a logic device, the study on optimal structure of FBFET was first performed in terms of reducing a memory window. Based on the N-type FBFET, the memory window was investigated with different values of doping concentration and length of channel region divided into two regions. The threshold voltage, capacitance, and transconductance of two cases of M3DIC composed with proposed FBFET were investigated for different thickness of an interlayer dielectric (TILD). In the Case 1, only for reverse sweep, the threshold voltage of FBFET in the tier2 was changed significantly at TILD < 15 nm, and the capacitance and transconductance of FBFET in the tier2 changed significantly at TILD < 20 nm, as bottom gate voltage applied with 0 and 1 V. In the Case 2, the electrical characteristics of FBFET in the tier2 changed greater than Case 1 with different TILD.

Variations in Electrical Characteristics of Near-Surface Atmosphere during Strong Earthquakes: Observation Results

Variations in Electrical Characteristics of Near-Surface Atmosphere during Strong Earthquakes: Observation Results

Fabrication and Characterization of Nanonet-Channel LTPS TFTs Using a Nanosphere-Assisted Patterning Technique.

We present the fabrication and electrical characteristics of nanonet-channel (NET) low-temperature polysilicon channel (LTPS) thin-film transistors (TFTs) using a nanosphere-assisted patterning (NAP) technique. The NAP technique is introduced to form a nanonet-channel instead of the electron beam lithography (EBL) or conventional photolithography method. The size and space of the holes in the nanonet structure are well controlled by oxygen plasma treatment and a metal lift-off process. The nanonet-channel TFTs show improved electrical characteristics in terms of the ION/IOFF, threshold voltage, and subthreshold swing compared with conventional planar devices. The nanonet-channel devices also show a high immunity to hot-carrier injection and a lower variation of electrical characteristics. The standard deviation of VTH (σVTH) is reduced by 33% for a nanonet-channel device with a gate length of 3 μm, which is mainly attributed to the reduction of the grain boundary traps and enhanced gate controllability. These results suggest that the cost-effective NAP technique is promising for manufacturing high-performance nanonet-channel LTPS TFTs with lower electrical variations.