Abstract
We present the fabrication and electrical characteristics of nanonet-channel (NET) low-temperature polysilicon channel (LTPS) thin-film transistors (TFTs) using a nanosphere-assisted patterning (NAP) technique. The NAP technique is introduced to form a nanonet-channel instead of the electron beam lithography (EBL) or conventional photolithography method. The size and space of the holes in the nanonet structure are well controlled by oxygen plasma treatment and a metal lift-off process. The nanonet-channel TFTs show improved electrical characteristics in terms of the ION/IOFF, threshold voltage, and subthreshold swing compared with conventional planar devices. The nanonet-channel devices also show a high immunity to hot-carrier injection and a lower variation of electrical characteristics. The standard deviation of VTH (σVTH) is reduced by 33% for a nanonet-channel device with a gate length of 3 μm, which is mainly attributed to the reduction of the grain boundary traps and enhanced gate controllability. These results suggest that the cost-effective NAP technique is promising for manufacturing high-performance nanonet-channel LTPS TFTs with lower electrical variations.
Highlights
Polysilicon thin-film transistors have been widely used in flat panel displays, image sensors, and 3D memory devices [1,2,3,4,5,6,7,8,9,10]
We demonstrated nanonet-channel low-temperature polysilicon (LTPS) thin-film transistors (TFTs) using the nanosphere-assisted patterning (NAP) technique
Nanonet-channel structure, the effective reduction of grain boundary (GB) traps and better gate controllability can lead to a thinner Wdep
Summary
Polysilicon thin-film transistors (poly-Si TFTs) have been widely used in flat panel displays, image sensors, and 3D memory devices [1,2,3,4,5,6,7,8,9,10]. The acceptor-like or donor-like traps in GBs can cause potentialbarrier fluctuations and interrupt the carrier flow in the channel [11,12]. Another important issue is the non-uniformity of the electrical performance caused by the size, number, and quality of GBs varied from device to device and wafer to wafer [13,14]. A macaroni channel structure demonstrated an improved performance for 3D memory devices. We demonstrated nanonet-channel low-temperature polysilicon (LTPS) thin-film transistors (TFTs) using the NAP technique. The impact of the nanonet-channel on the variation of electrical characteristics was investigated
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