Threshold Voltage Values Research Articles

Amorphized length and variability in phase-change memory line cells.

The dimensions of amorphized regions in phase-change memory cells are critical parameters to design devices for different applications. However, these dimensions are difficult to be determined by direct imaging. In this work, the length of amorphized regions in multiple identical Ge2Sb2Te5 (GST) line cells was extracted from electrical measurements. After each cell was programmed to an amorphous state, a sequence of increasing-amplitude post-reset voltage pulses separated by low-amplitude read DC sweeps was applied. When a post-reset voltage pulse with sufficient amplitude was applied to a given cell, the measured current and the post-pulse resistance increased drastically, indicating that the cell re-amorphized after threshold switching, melting, and quenching. The amorphized length was calculated using the measured voltage at which the threshold switching occurred and the expected drifted threshold field at that time. The measured threshold voltage values and, hence, the extracted amorphized length, generally increase linearly with the programmed resistance levels. However, significant variability arises from the intrinsically unique crystallization and amorphization processes in these devices. For example, cells programmed to an amorphous resistance of approx. 50 MΩ show threshold voltage values of 5.5–7.5 V, corresponding to amorphized length values of 290–395 nm. This unpredictable programming feature in phase-change memory devices can be utilized in hardware security applications.

Physico-chemical and electro-optical properties of liquid crystals doped with chemically modified nanocline minerals

The object of study is nematic and smectic (ferroelectric) liquid crystals containing chemically modified nanoclay based on montmorillonite. The aim of the work is to develop new composite materials with improved physico-chemical and electro-optical properties. During the study, chemical methods were developed for modification of the surface of nanoclay; the mesomorphic, dielectric, and electro-optical properties of nematic and ferroelectric compositions doped with a nanoclay with a modified surface are studied. On the basis of experimental data, the regularities of the influence of functional groups grafted onto the surface of nanoclay on the mesomorphic, dielectric and electro-optical properties of nematic and ferroelectric compositions are established. It has been shown experimentally that the addition of a small amount of nanoclay to a nematic and ferroelectric liquid crystal material can significantly improve the electro-optical response time and reduce the threshold and saturation voltage values. For ferroelectric liquid crystals, the addition of nanoclay leads to an increase in the tilt angle in the layer and an increase in spontaneous polarization.

Toward ultraviolet solution processed ZrOx/IZO transistors with top-gate and dual-gate operation: Selection of solvents, precursors, stabilizers, and additive elements

Low-temperature processed oxide thin-film transistors (TFTs) have been developed by the process of solution-processed metal oxide films using deep ultraviolet (UV) irradiation, although they still suffer from relatively poor electrical performance and severe electrical and chemical instability. This UV coating solution essentially involves chemical damage from acidic or basic precursor ligands; therefore, the top-gate and dual-gate TFTs suffer structurally inherent chemical damage, which limits the freedom of process design. An engineering concept solution using the four functional components of solvent, precursor, stabilizer, and additive was suggested for UV solution coating of high-k zirconium oxide (ZrOx). Here the proposed solvent, stabilizer, precursor, and additive include polar-aprotic N,N-methylformamide, zirconium acetylacetonate, ethanolamine, and oleic acid for polar-aprotic solution, effective photolysis, complete precursor dissolution, and high densification, respectively. The ultrathin ZrOx (15 nm) revealed a low leakage current density of <10−11 mA/cm2 at 1 MV/cm, good breakdown voltage, and a constant capacitance of approximately 260 nF/cm2 at 1 MHz. Similar transfer characteristics of both the bottom and top gates, and a field-effect mobility of 24 cm2/V, without degradation of subthreshold swing and threshold voltage values in the dual-gate, were involved in the chemically durable process and the dense coating conditions of ZrOx, regardless of the IZO and ZrOx stacking sequence.

A new analytical approach to threshold voltage modeling of triple material gate-all-around heterojunction tunnel field effect transistor

This paper presents a novel threshold voltage model for triple material gate-all-around TFET based on its surface potential that also includes the device depletion regimes. Analytical expressions for surface potential are derived using 2D Poison’s equation and parabolic approximation method. Electric Field and threshold voltage of the device are derived by considering the surface potential of source channel depletion regime. Threshold voltage roll off is then obtained by subtraction between short channel TFET and long channel TFET. Drain-induced barrier lowering of the proposed device is achieved using threshold voltage values for two different drains to source voltage values. Threshold voltage lies in a range between 0.6 and 0.8 V for different doping concentrations as obtained from simulation, which is less in comparison with other available TFET devices. The validity of the device model is tested using TCAD ATLAS Simulation tool.

Electrical conductivity and breakdown properties of some erbium oxide doped phosphovanadate glasses

Electrical conductivity and breakdown properties have been investigated for 70%V2O5·(30–x)%P2O5·x%Er2O3 glasses with (0 ≤ x ≤ 0.9). The conductivity measurements are carried out at frequency range from 80 to 3 × 106 Hz, and at temperature range from 303 to 463. The dc electrical conductivity (σdc) and dc activation energy (Edc) are shown to be relatively sensitive to the composition. σdc is found to vary between 3 × 10−4 and 0.024 Ω−1 m−1, and Edc is estimated to be in the range 0.36–0.44 eV. On the other hand, σac is found to vary between 7 × 10−4 and 0.15 Ω−1 m−1. Both σdc and σac are discussed according to the multi phonon hopping process of weak electron-lattice coupling, they are found to be proportional to Tpwith the exponent p between 11.5 and 13.15. All the samples exhibit a threshold type switching with a maximum current of about 3 mA. All the samples are found to present breakdown properties at different critical voltages. The threshold voltage (Vth) values are affected by ambient temperature, sample thickness and composition ratio. Measured surface temperature during the switching cycles and the calculated core temperature confirm the repeatedly switching of the samples without any internal thermal destruction occur.

Design of Efficient Ternary Operators for Scrambling in CNTFET Technology

Digital computation using ternary logic allows compact and energy-efficient digital design due to the reduction in circuit interconnects and chip area. CNFET unique characteristic of scalable threshold voltage value by utilizing the CNTs of different chirality vectors makes it a suitable option to realize ternary logic designs. This work presents hardware-efficient and low-power ternary operators exclusively used for scrambling applications in crypto-algorithms. The proffered designs are based on multiplexing the output digits among various unary cycle operators as the input trits. Extensive HSPICE simulations are conducted using standard 32-nm CNFET Stanford model to calculate the performance parameters of the proposed circuits. The presented designs show a significant improvement in terms of average power consumption, component count and energy consumption as compared to earlier counterparts. Results for various proposed scrambling operators Sop3, Sop4 and Sop5 show about an average reduction in energy consumption of 80% as compared to previously presented scrambling operators. Moreover, the Monte Carlo simulation results reveal that the proposed designs are robust against the mismatches in the diameter of CNTs.

(Keynote) Gate-All-Around Nanowire & Nanosheet FETs for Advanced, Ultra-Scaled Technologies

As two-dimensional CMOS scaling is reaching its physical limits, maintaining profitable node-to-node cost-per-transistor gains requires increasingly constraining design restrictions. To help preserve the power, performance, area, and cost (PPAC) logic roadmap several innovations are being explored, such as cell height reduction by decreasing the number of metal tracks. This allows compensating for the recent trend of a more modest pitch scaling, but it also requires fin depopulation from two fins to one fin per finFET transistor for ultra-scaled cells with reduced number of metal tracks [1,2], which impacts the device performance. As such, in order to keep the scaling gains, introduction of novel device architectures is needed, with gate-all-around (GAA) nanowire (NW) or nanosheet (NS) FETs [2-8] being regarded as the most promising finFET replacements for advanced nodes (Fig. 1). These devices provide better electrostatics allowing further gate length (Lgate) scaling, with NS offering higher current drivability (ION) per layout footprint than NW thanks to larger effective widths (Weff). Furthermore, by having the option to vary the NS Weff on the same chip/wafer, this enables additional design flexibility, typically targeting wider NS for high performance computing and narrower NS for low power applications [5,7,8]. At the same time, vertically stacking several NS enables further boosting ION at the expense of an increase in parasitic capacitance. Minimizing the latter is crucial for delivering both optimal performance and power efficiency. That can be achieved by reducing the vertical distance between the stacked lateral NS as demonstrated in Fig. 2 and via the implementation of inner spacers in-between them [2,6]. Both features introduce considerable challenges for device fabrication. However, it still shares many of the building blocks of a finFET flow thus allowing a smoother technological transition for manufacturing as compared to other device architectures. In the case of the NS vertical pitch, its shrinkage requires scaled Si/SiGe-multilayer stacks growth and thinner gate stacks that can be implemented with the guarantee of similar gate control on all NS surfaces. That has been demonstrated for a stack with an alternative, thinner (<2.5nm) n-type effective work function (EWF) metal layer yielding tight, low threshold voltage values (VT < 0.2V - NMOS), while showing improved noise and reliability behavior [9].Another GAA device architecture, with vertical NW or NS (VNW/VNS) and vertically defined Lgate, has been shown to have the potential to enable denser and more energy efficient SRAMs and MRAMs when used as the cell transistors or selector, respectively [10-13]. In the overall scaling roadmap, the latter type of memory has been gaining increased momentum as an alternative for enabling large, ultra-high-density last-level caches for systems with reduced area and energy. Overall, GAA VNW/VNS FETs represent a more disruptive technological transition, moving from 2D to 3D layouts. Nevertheless, they can also open new scaling paths in the third dimension. In this context, the feasibility of co-integrating on the same wafer and in a cost-effective way finFETs (or GAA lateral NS FETs) for high performance logic and GAA VNS FETs as MRAM selector is evaluated by process simulations, experimentally validated for each type of devices (Fig. 3). In this scheme, cost adders were minimized by sharing the maximum number of critical process steps for both FETs. A replacement metal gate process, standardly used in finFETs and lateral NS FETs can be also advantageous for VNS FETs as it can allow shrinkage of the channel cross-section for improved electrostatics (without impacting the bottom/top S/D [14]), while also enabling new techniques for stress-induced mobility enhancement [12]. Specific for VNS FETs, a self-aligned gate electrode can be easily implemented by relying on the different oxidation kinetics of Si and SiGe and using SiGe/Si/SiGe instead of Si-only pillars.

Influence of Fast Neutron Irradiation on the Electrical and Optical Properties of Li Doped ZnSnO Thin Film Transistor

The effects of fast neutron irradiation on the electrical and optical properties of Li (3 at%) doped ZnSnO (ZTO) thin films fabricated using a sol-gel process are investigated. From the results of Li-ZTO TFT characteristics according to change of neutron irradiation time, the saturation mobility is found to increase and threshold voltage values shift to a negative direction from 1,000 s neutron irradiation time. X-ray photoelectron spectroscopy analysis of the O 1s core level shows that the relative area of oxygen vacancies is almost unchanged with different irradiation times. From the results of band alignment, it is confirmed that, due to the increase of electron carrier concentration, the Fermi level (EF) of the sample irradiated for 1,000 s is located at the position closest to the conduction band minimum. The increase in electron concentration is considered by looking at the shallow band edge state under the conduction band edge formed by fast neutron irradiation of more than 1,000 s.

Effect of intermolecular charge transfer between Ni(II)Pc and CdSeS/ZnS QD on dielectric relaxation mechanism of 5CB nematic liquid crystals in the presence of UV illumination

This paper is a report on electro-optical and dielectric parameters of Ni(II)Pc (nickel(II) phthalocyanine) and CdSeS/ZnS (cadmium selenide sulfide/zinc sulfide) quantum dot (QD) doped 5CB (4-pentyl-4′-cyanobiphenyl) nematic liquid crystal (LC) in the dark and under UV illumination condition. Electro-optical and dielectric measurements of the samples were carried out using electro-optical switching and dielectric spectroscopy methods, respectively. Dielectric anisotropy, relaxation frequency, dielectric strength, and threshold voltage values were determined using the experimental data. Investigation of dielectric properties demonstrates that relaxation frequency is decreased because of the dispersal of Ni(II)Pc and CdSeS/ZnS QD under UV exposure. The electro-optical investigation also shows that UV illumination and dispersal of Ni(II)Pc and CdSeS/ZnS QD cause a decrease in threshold voltages. Overall, results indicate that Ni(II)Pc, CdSeS/ZnS QD and UV light enhanced the electro-optical and dielectric properties of 5CB nematic LC.

Study of nanocrystalline silicon-germanium for the development of thin film transistors

In this work, we study the effect of the deposition RF-power on the structural, optical and electrical properties of hydrogenated nanocrystalline silicon-germanium (nc-SiGe:H) thin films obtained by plasma enhanced chemical vapor deposition (PECVD) at substrate temperature of 200 °C. The objective is to produce films with high crystalline fraction in order to be used as active layers in thin film transistors (TFTs). Bottom-gate (BG) thin film transistors were fabricated with nc-SiGe:H active layers, deposited at different RF-power. Values of ON-OFF current ratio, subthreshold slope and threshold voltage of 105, 0.12 V/dec and 0.9 V, respectively, were obtained on TFTs with the nc-SiGe:H active layer deposited at 25 W.

High Performance Transparent a-IGZO Thin Film Transistors With ALD-HfO2 Gate Insulator on Colorless Polyimide Substrate

High performance and transparent amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFT) have been successfully fabricated on the colorless polyimide plastic substrate using a high quality HfO2 dielectric film formed by the low temperature atomic layer deposition process as the gate insulator. Besides, the effects of source/drain material, ITO film and Mo metal, are also studied and compared in this work. With the optimized process condition, the devices with ITO source/drain exhibit a high ION/IOFF current ratio of ~4.25 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> , a lower sub-threshold swing value of 0.087 V/decade, a desirable positive threshold voltage value of 0.1379 V and an acceptable field effect mobility of 19.69 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs. while it also shows excellent reliability characteristic and low hysteresis. These results may appear highly promising potentials for the next generation fully transparent flexible display application.

Quantum transport of tunnel field effect transistors based on bilayer-graphene nanoribbon heterostructures

Abstract We examine quantum transport properties of a graphene system with several different configurations, which the scatter region and two semi-infinite electrodes are represented by single-layer graphene nanoribbons (SGNR) and bilayer graphene nanoribbons (BGNR) with zigzag edge and armchair edge, geometrically known as a GNR field-effect transistor (GNR-FET). Here, the SGNR/BGNR/SGNR (C2 and C3) and BGNR/SGNR/BGNR (C4) configurations are introduced. The transmission process is the vertical tunneling for the configuration based on C3 heterojunction, while in other configurations should be mostly in-plane, that occurs vertically in the device. The calculations are based on the recursive Green’s function theory within the tight-binding method in the coherent regime. Here, we aim to design high performance ternary by using GNR tunneling field-effect transistors (GNR-TFET). Our numerical results show a metal–semiconductor transition in the SGNR/BGNR heterostructure with sizeable band gap value due to a vertical hopping between the both layers in the BGNR device. Also, the strong configuration-dependent Van Hove singularities appear at different energies in the semi-one-dimension TFET. The findings show that the C1 and C3 configurations deliver the largest and the smallest current up to about 1.4 V among four configurations. Moreover, the gate voltage can control and modulate the C3 configuration more than the others with the ON-current modulated effectively. The value of threshold voltage depends significantly on the vertical hopping parameter for the C3 configuration of the nanoribbon with width of N a = 14 . By controlling the geometrical parameters of the system, the ON–OFF current ratio can be tuned. Our numerical results may serve as a base in designing electronic devices based on graphene structure.

Impact of stress effect on triple material gate step-FinFET with DC and AC analysis

Step-FinFET is an improvisation in various electrical characteristics with a modified mechanism. The gate length 20 nm, 15 nm, 20 nm has allowed an acceptable driving current and considerable power consumption which longer the battery life. The study consist of electron density, electron velocity, mobility, electric field, and surface potential to relate the improved device performance. The major variation of drain current due to stress effect, tunneling, saturation factor, and minority factor has been investigated. This paper analyzes the parameters like transconductance (Gm), Drain conductance (gd), input capacitance (Cgg), cut off frequency (fT), power consumption, etc., for verifying the RF and analog application. Various short channel effect (SCE) also studied in terms of threshold voltage (Vth), sub-threshold swing (SS), drain induced barrier lowering (DIBL) and On/Off ratio are investigated with different gate length and drain bias. As a result the minimum values of threshold voltage, SS and DIBL calculated for gate length of 15 nm are 0.2426 V, 69 mV/dec, 14.6 mV/V, respectively.

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

AbstractIn this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (VGS) value for pull‐down units. The results showed all the VOUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable VOUT voltage when the threshold voltage for all TFTs was changed from −6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved VOUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.

Indium Zinc Oxide Thin-Film Transistors with Ultraviolet Post-Annealing Treatment.

Ultraviolet treatment (UV) light was performed for indium zinc oxide thin-film transistors (TFTs) for different time so as to study the effects of post-annealing on electrical characteristic of TFTs. Electrical characteristic results proved that the value of high mobility after UV post-annealing process (2 mW/cm². for 30 s was obviously enhanced, and it had an acceptable on/off ratio, reasonable threshold voltage, and subthreshold swing. Among them, the value of the electronic mobility is 2.41 cm²/Vs, the threshold voltage value is 8.31 V, the on/off current ratio value is 2×2 × 105, and the subthreshold swing value is 1.13 V/dec.

48.1: Invited Paper: A Novel Gate Driver Circuit for Depletion Mode a‐IGZO TFTs

This paper proposes a novel gate driver circuit to realize high reliability using depletion mode a‐InGaZnO thin‐film transistors (TFTs). Using 3T1C circuit configuration, we prevented the leakage path for Q node by realizing gate‐to‐source voltage (VGS) under 0 V value. The proposed circuit can be operated when the VTH is shifted to ‐3 V from the initial value (VTH= ‐0.35 V). Also, the novel gate driver circuit with the AC driven pull‐down units can maintain the almost same normalized value from ‐1 V to ‐3 V of the VTH shift range when compared to the results of circuit with the DC driven pull‐down units. The proposed circuit can maintain the power consumption within 3.65 times of the normal value at ‐5 V threshold voltage value.

Eutectic Sb7.4Te92.6 thin film for non-volatile phase-change memories

PurposeThe purpose of this paper is to investigate the structure and electrical properties of eutectic Sb7.4Te92.6 as made thin films to evaluate their potentiality for application to non-volatile phase-change memories.Design/methodology/approachThe films were prepared by the pulsed laser deposition technique. The films were characterized by using X-ray diffraction in grazing-incident geometry, differential scanning calorimetry, Raman spectroscopy and transversal current–voltage curves.FindingsThe memory effect state, characteristic of a typical phase-change memory material, was observed. The temperature of crystallization was about 100ºC.Research limitations/implicationsFurther studies on endurance, scaling and SET/RESET operations are needed.Practical implicationsOne of the main characteristic values, the hold voltage and the threshold voltage values, were about 0.85 and 1.2 V, respectively, in a line with those of Ge2Sb2Te5, GeTe and Sb2Te being considered to date as the main compounds for phase-change memory devices.Originality/valueThe conduction mechanism in the amorphous regime is highly agreed with the Poole–Frenkel effect in deep traps.

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

Approach for MVL design based on armchair graphene nanoribbon field effect transistor and arithmetic circuits design

This paper presents the approach for multiple-valued logic (MVL) design and implementing the arithmetic circuit based on armchair graphene nanoribbon field effect transistors (GNRFETs). For this purpose, the values of the threshold voltages are obtained for GNRFETs for utilizing in MVL. The Id-Vgs curve is drawn for all n-type GNRFETs by Synopsys HSPICE tools. Moreover, the width variations and band gap energy are scrutinized. The value of threshold voltage for range of N ​= ​3p+1 is more than N ​= ​3p. These observations exhibit that variation of the threshold voltages can be utilized for a circuit design based on GNRFET. Furthermore, the sub-threshold swing is obtained. As a proof of the concept, the ternary arithmetic circuits based on GNR are designed with 0.5 ​V supply voltage. The computational results confirm the threshold voltages values as well as the suitable figure of merits of using GNRFETs in multiple-valued logic circuit design.