48.1: Invited Paper: A Novel Gate Driver Circuit for Depletion Mode a‐IGZO TFTs

Abstract

This paper proposes a novel gate driver circuit to realize high reliability using depletion mode a‐InGaZnO thin‐film transistors (TFTs). Using 3T1C circuit configuration, we prevented the leakage path for Q node by realizing gate‐to‐source voltage (VGS) under 0 V value. The proposed circuit can be operated when the VTH is shifted to ‐3 V from the initial value (VTH= ‐0.35 V). Also, the novel gate driver circuit with the AC driven pull‐down units can maintain the almost same normalized value from ‐1 V to ‐3 V of the VTH shift range when compared to the results of circuit with the DC driven pull‐down units. The proposed circuit can maintain the power consumption within 3.65 times of the normal value at ‐5 V threshold voltage value.