Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

Abstract

This paper introduces novel driving methods of the pull-down unit in a gate driver circuit for enhancement- and depletion-mode a-IGZO thin-film transistors (TFTs). The proposed gate driver circuit can achieve uniform output characteristics and effectively reduce the $\text{V}_{\mathrm{ OUT}}$ ripple voltage because the threshold voltage ( $\text{V}_{\mathrm{ TH}}$ ) of the pull-down units is compensated regardless of the a-IGZO TFT operation characteristics (enhancement mode: positive value of $\text{V}_{\mathrm{ TH}}$ , depletion mode: negative value of $\text{V}_{\mathrm{ TH}}$ ). Many groups proposed the $\text{V}_{\mathrm{ TH}}$ compensation method for pull-down TFTs in the gate driver circuit using a diode connection structure. However, the diode connection structure to extract the $\text{V}_{\mathrm{ TH}}$ value cannot be applied in the depletion-mode oxide TFTs because TFT enters the turn-on state even when the $\text{V}_{\mathrm{ GS}}$ value is 0 V. To solve this problem, we adopted the $\text{V}_{\mathrm{ TH}}$ extraction period only once in one frame time. As a result, our circuit can compensate for $\text{V}_{\mathrm{ TH}}$ of the pull-down unit in the enhancement mode and can be normally operated in the depletion mode. Adjunctively, two low signals (VGL1 and VGL2) and QC node were designed to prevent the leakage current path for Q and $\text{V}_{\mathrm{ OUT}}$ nodes. To verify the threshold voltage tolerance for various stress conditions, we demonstrated the reliability of the circuit according to the threshold voltage change of the TFTs. The simulation result shows that all the $\text{V}_{\mathrm{ OUT}}$ waveforms are maintained at +28 V (VGH) under the $\text{V}_{\mathrm{ TH}}$ shift conditions from −7 V to +11 V; further, the rising time and falling time are less than $0.62~{\mu }\text{s}$ and $0.96~{\mu }\text{s}$ , respectively. Based on a 120-Hz ultra-high definition (UHD) graphics ( $3840{\times }2160$ ) display panel, the proposed circuit has uniform $\text{V}_{\mathrm{ OUT}}$ characteristics compared to previous $\text{V}_{\mathrm{ TH}}$ compensation circuit when $\Delta \text{V}_{\mathrm{ TH}}$ changes from −3 V to +11 V. When $\Delta \text{V}_{\mathrm{ TH}}$ changes from −4 V to −7 V, there is also no circuit malfunction, even with slight increase in the falling time and power consumption.