Design of Efficient Ternary Operators for Scrambling in CNTFET Technology

Abstract

Digital computation using ternary logic allows compact and energy-efficient digital design due to the reduction in circuit interconnects and chip area. CNFET unique characteristic of scalable threshold voltage value by utilizing the CNTs of different chirality vectors makes it a suitable option to realize ternary logic designs. This work presents hardware-efficient and low-power ternary operators exclusively used for scrambling applications in crypto-algorithms. The proffered designs are based on multiplexing the output digits among various unary cycle operators as the input trits. Extensive HSPICE simulations are conducted using standard 32-nm CNFET Stanford model to calculate the performance parameters of the proposed circuits. The presented designs show a significant improvement in terms of average power consumption, component count and energy consumption as compared to earlier counterparts. Results for various proposed scrambling operators Sop3, Sop4 and Sop5 show about an average reduction in energy consumption of 80% as compared to previously presented scrambling operators. Moreover, the Monte Carlo simulation results reveal that the proposed designs are robust against the mismatches in the diameter of CNTs.