Use Of Test Structures Research Articles

Sputtering of redeposited material in focused ion beam silicon processing

Sputtering of the redeposited material was experimentally studied with the use of test structures specially prepared by the focused beam of gallium ions with different energies. The consequent milling of the structures and their characterization utilizing transmission electron microscopy revealed that the milling rate for the redeposited material is 1.3 times higher than for crystalline silicon. The dynamic Monte-Carlo simulations of sputtering were performed with the introduced discrete-continuous variation model for the surface binding energy of the silicon atoms, which takes into account the formation of the gallium precipitates in the surface layer of the bombarded material. The calculations allowed obtaining not only the correct values of redeposited material milling rate, but also the distributions of gallium atoms in the sputtered materials which were in the qualitative agreement with the experimental data.

The Use of Test Structures to Perform Chip Level Characterization Studies of Ni and NiFe Electrochemical Deposition

This paper describes the first use of test structures designed to characterize the fundamental properties of nickel and nickel-iron alloy films deposited using electroplating. The structures are used to perform a chip-level investigation into the effects of electrolyte bath composition on the characteristics of deposited films. The advantage of this methodology is that each electrolyte change does not require the replacement of the large volume bath associated with wafer scale manufacturing investigations, thereby, making the characterisation and optimization of electroplating baths far less time consuming, and considerably more cost effective.

An analytic procedure for extraction of metallic collector-up InP/InGaAsP/InGaAs HBT small signal equivalent circuit parameters

A parameter extraction procedure for determining an improved T-topology small signal equivalent circuit of a metallic collector-up HBT with composite base is presented. The proposed T-small signal equivalent circuit includes base and collector impedances modelled by parallel RC circuits. The new technique employs analytically derived expressions for direct calculation of HBT T-Model equivalent circuit element values in terms of the measured S-parameters. This approach avoids errors due to uncertainty in fitting to large, over determined equivalent circuits and does not require the use of test structures and extra measurement steps to evaluate parasitics. Physically realistic results are demonstrated under various biasing conditions for the n–p–n InP/InGaAsP/InGaAs composed base HBT with metallic collector-up structure (C-up MHBT). The agreement between the measured and model-produced data is excellent over the large frequency range and for several polarizations conditions for devices.

Extraction of the InP/InGaAs metallic collector-up heterojunction bipolar transistor small-signal equivalent circuit

An efficient technique for determining the small-signal equivalent-circuit model of a Metal collector-up Heterojunction Bipolar Transistor (C-up MHBT) is presented. The technique employs analytically derived expressions for direct calculation of HBT T-Model equivalent circuit element values in terms of the measured S-parameters. This approach avoids errors due to uncertainty in fitting to large, over determined equivalent circuits and does not require the use of test structures and extra measurement steps to evaluate parasitics. Physically realistic results are demonstrated under various biasing conditions for the n-p-n InP/InGaAs HBT with metallic collector up structure. The agreement between the measured and model-produced data is excellent over the large frequency range and for several polarizations conditions for devices.

Analysis of external latch-up protection test structure design using numerical simulation

With each new CMOS technology the latch-up sensitivity and eAects of prevention strategies change. Products built in these technologies must adhere to stringent guidelines for latch-up ‘Hardness’, and for this reason characterisation of new technologies is needed through the use of test structures. This paper shows a numerical simulation approach which can determine the relative eAectiveness of guard-rings in ESD protection device test structures. In this work, time taken to characterise latch-up protection test structures and to chose a protection strategy is greatly reduced by using numerical simulations to design the test structures. The results presented are for variations to the guard-rings for two technologies. Included in these are the typical simulation times and resources required. The technique outlined has the joint advantages of providing accurately representative simulations of the technology and test structure layout in a practical time frame. # 1999 Elsevier Science Ltd. All rights reserved.

Accurate high speed empirically based predictive modeling of deeply embedded gridded parallel plate capacitors fabricated in a multilayer LTCC process

A novel technique is presented for the accurate, rapid, high frequency, predictive modeling of parallel plate capacitors with gridded plates manufactured in a multilayer low temperature cofired ceramic (LTCC) process. The method is empirical in nature and is based on the concept of incrementally constructing the model for a structure from well characterized individual building blocks. Building blocks are characterized by the use of test structures and measurements, and are modeled using passive lumped circuit elements. This method is applied to the predictive modeling of deeply embedded gridded parallel plate capacitor structures. The procedure has been experimentally verified, with accurate predictions of behavior obtained up to the second self resonance for large area gridded parallel plate capacitors. Since lumped element circuits are generated by this method, structure prediction speed is determined by circuit size and simulator small signal analysis time. The method is versatile and is well suited for circuit design applications.

Use of test structures for characterization and modeling of inter- and intra-layer capacitances in a CMOS process

In this paper, we present a global approach for inter- and intralayer capacitance characterization and modeling. Using an accurate on-chip measurement method, we have characterized realistic test patterns, i.e., test patterns consistent with capacitive couplings encountered in a layout. These reference values have allowed us to point out some limitations of current models and to propose new simple analytical models suitable for small dimension capacitive patterns. This paper emphasizes inter- and intralayer modeling.

Review of semiconductor microelectronic test structures with applications to infrared detector materials and processes

The impact of microelectronic test structures, as they have been applied to silicon integrated circuits (ICS) and gallium arsenide monolithic microwave integrated circuits (MMICS), is reviewed. General principles for the use of test structures with possible applications to infrared (IR) detector technology based on HgCdTe and other materials are emphasized. The uses of test structures for Si and GaAs, test chip design methodology and some examples of how test structures have been applied for process control and to increase yield are discussed. Specific test structures and techniques that have been applied to IR detectors are also reviewed. The basic design considerations and measurements possible with each class of test structure are discussed. The important experience of the Si and GaAs industries, applicable to IR detectors, is that significant yield improvement is possible with improved process control using test structures. Increased research efforts to expand the applications of test structures to IR detector manufacture are indicated.

Evaluation of the factors determining HBT high-frequency performance by direct analysis of S-parameter data

A novel parameter extraction formalism for the evaluation of heterojunction bipolar transistor (HBT) device physics is presented. The technique uses analytically derived expressions for direct calculation of the HBT T-model equivalent circuit element values in terms of the measured S-parameters. All elements are directly calculated with the exception of the emitter leg of the T-model. This approach avoids errors due to uncertainty in fitting to large, overdetermined equivalent circuits, and does not require the use of test structures and extra measurement steps to evaluate parasitics. Detailed bias-dependent results for the directly calculated circuit elements are presented. An analysis of the short circuit current gain that separates the transit times and RC products and allows evaluation of their individual contribution to the measured f/sub T/ and significance in limiting the HBT's high-frequency performance is reported. >

Use of test structures in the production of CdS/Cu 2S photovoltaic devices

The usefulness of a test structure as a tool in the manufacture of large-area CdS/Cu 2S solar cell arrays is shown. The electrical parameters measured on the test structure are presented as an isometric density plot which yields a global image of the photovoltaic quality of the substrate used.

Use of test structures and results of electrical tests for silicon-on-sapphire integrated circuit processes

Use of test structures and results of electrical tests for silicon-on-sapphire integrated circuit processes

Use of test structures and results of electrical tests for silicon-on-sapphire integrated circuit processes

To obtain parametric data characterizing an IC processing schedule, a pattern of specialized test devices was used in conjunction with a powerful computer-controlled testing and data-reduction system. A test programming system which allows looping and branching was used to control instrumentation having capacitance measurement capability in addition to the usual voltage and current instrumentation. The test devices (MOS capacitor, transistor, and various other types) were tested automatically using the system. Computer-based data logging, analysis, and display generation techniques were necessary so the large bulk of data taken could be-reduced to physically meaningful parameters whose significance can be readily comprehended. In addition to the usual statistical analysis methods, a perspective three-dimensional plot showing parameter values as a function of position in the wafer plane was found most valuable. This data generation system is felt to be a necessary step to providing a complete characterization of both the capabilities and limitations of an IC fabrication scheme, which is vital to both the circuit designer and the line process engineer.

The application of test structures for the study of surface effects in LSI circuitry

The successful development of LSI circuitry with multilevel metallization requires the development of practical means for insuring the highest level of performance and reliability. This requires the development of a broad fundamental understanding of the factors that affect the semiconductor-insulator interface and of practical means for measuring the fundamental properties of this Interface. A comprehensive model has been developed that includes each of the known factors that influences the electrical properties of the semiconductor-insulator interface. The design and use of test structures for measuring the effects of each of these factors are discussed. Test structures are shown to be useful for the preliminary evaluation, development, and control of materials, techniques, equipment, and processes, and for reliability assessment. The test structures are useful in connection with both MOS and bipolar circuits and over the entire range of circuit complexity. Effects of variations in materials or processes on the electrical properties of the interface are given. Experimental data are given that demonstrate the utility of test structures for the evaluation of materials, process, and structural designs, and for production controls and reliability assessment.