Use of test structures and results of electrical tests for silicon-on-sapphire integrated circuit processes

Abstract

To obtain parametric data characterizing an IC processing schedule, a pattern of specialized test devices was used in conjunction with a powerful computer-controlled testing and data-reduction system. A test programming system which allows looping and branching was used to control instrumentation having capacitance measurement capability in addition to the usual voltage and current instrumentation. The test devices (MOS capacitor, transistor, and various other types) were tested automatically using the system. Computer-based data logging, analysis, and display generation techniques were necessary so the large bulk of data taken could be-reduced to physically meaningful parameters whose significance can be readily comprehended. In addition to the usual statistical analysis methods, a perspective three-dimensional plot showing parameter values as a function of position in the wafer plane was found most valuable. This data generation system is felt to be a necessary step to providing a complete characterization of both the capabilities and limitations of an IC fabrication scheme, which is vital to both the circuit designer and the line process engineer.