Upset Cross Section Research Articles

Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

This paper shows the impact of low linear energy transfer heavy ions on the reliability of 28-nm Bulk static random access memory (RAM) cells from Artix-7 field-programmable gate array. Irradiation tests on the ground showed significant differences in the multiple bit upset cross section of configuration RAM and block RAM memory cells under various angles of incidence and rotation of the device. Experimental data are analyzed at transistor level by using the single-event effect prediction tool called multiscale single-event phenomenon prediction platform coupled with SPICE simulations.

A calculation method to estimate single event upset cross section

We calculate single event effect cross-section with a new general method based on the evaluation of the current collected by an electrode and the ability of the cell to dissipate the charge involved in the event. Basically, a part of the charge deposited by an ionizing particle is collected, and a part of this latest is dissipated during the transient. The approach allows explaining experimental cross section obtained for heavy ions irradiations. Moreover, the use of heavy ions experimental results allow predicting the single event crosses section for protons.

A comparison of heavy ion induced single event upset susceptibility in unhardened 6T/SRAM and hardened ADE/SRAM

Single event upset (SEU) susceptibility of unhardened 6T/SRAM and hardened active delay element (ADE)/SRAM, fabricated with 0.35μm silicon-on-insulator (SOI) CMOS technology, was investigated at heavy ion accelerator. The mechanisms were revealed by the laser irradiation and resistor-capacitor hardened techniques. Compared with conventional 6T/SRAM, the hardened ADE/SRAM exhibited higher tolerance to heavy ion irradiation, with an increase of about 80% in the LET threshold and a decrease of ∼64% in the limiting upset cross-section. Moreover, different probabilities between 0→1 and 1→0 transitions were observed, which were attributed to the specific architecture of ADE/SRAM memory cell. Consequently, the radiation-hardened technology can be an attractive alternative to the SEU tolerance of the device-level.

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets in a NAND Flash Memory

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found that the single-event upset (SEU) cross section varied inversely with cumulative fluence. We attribute the effect to the variable upset sensitivities of the memory cells. Furthermore, the effect impacts only single cell upsets in general. The rate of multiple-bit upsets remained relatively constant with fluence. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, traditional SEE testing techniques may underestimate the on-orbit event rate for a device with variable upset sensitivity.

Estimating Single-Event Logic Cross Sections in Advanced Technologies

Reliable estimation of logic single-event upset (SEU) cross section is becoming increasingly important for predicting the overall soft error rate. As technology scales and single-event transient (SET) pulse widths shrink to widths on the order of the setup-and-hold time of flip-flops, the probability of latching an SET as an SEU must be reevaluated. In this paper, previous assumptions about the relationship of SET pulsewidth to the probability of latching an SET are reconsidered and a model for transient latching probability has been developed for advanced technologies. A method using the improved transient latching probability and SET data is used to predict logic SEU cross section. The presented model has been used to estimate combinational logic SEU cross sections in 32-nm partially depleted silicon-on-insulator (SOI) technology given experimental heavy-ion SET data. Experimental SEU data show good agreement with the model presented in this paper.

Single event upset characteristics and physical mechanism for nanometric SOI SRAM induced by space energetic ions

Based on Monte-Carlo method, the characteristics and physical mechanisms for deposited-energy spectra in sensitive volume (SV), single event upset cross sections, and on-orbit error rates in 65-32 nm silicon-on-insulator static random access memory (SOI SRAM) devices induced by space energetic ions are investigated. Space ions on geostationary earth orbit exhibit a flux peak at an energy point of about 200 MeV/n. In consequence, the single event response of nanometric SOI SRAMs under 200 MeV/n heavy ions is studied in detail. The results show that 200 MeV/n space ions exhibit the large straggling of deposited-energy in the device SV with thickness ranging from 60 nm to 40 nm, which causes the single event upsets to occur in the sub-LETmth region. The device SV can only partially collect the electron-hole pairs in the single ion track with a wide distribution of secondary electrons. As a result, the maximum and average deposited-energy in the SV decrease by 25% and 33.3%, respectively. Further, the single event upset probability decreases and the on-orbit error rate decreases by about 80%. With the downscaling of feature size, the per-bit saturated cross sections and on-orbit error rates of nanometric SOI SRAM devices decrease dramatically. The phenomenon of constant-increasing single event upset cross section with higher ion linear energy transfer (LET) is not observed, owing to the fact that (a) the density of electron-hole pairs in the track of 200 MeV/n space ion is relatively low and (b) the SOI device has thin sensitive volume, which results in the fact that the secondary-electron effect cannot upset nearby sensitive cells. Besides, it is found that the direct-ionization process of trapped protons leads to an increase of on-orbit error rate of 65 nm SOI SRAM by one to two orders of magnitude.

Analysis of Bulk FinFET Structural Effects on Single-Event Cross Sections

A set of upset criteria based on circuit characteristic switching time frame is developed and used to bridge transistor-level TCAD simulations to circuit-level single-event (SE) upset cross sections for advanced (fast and small) digital circuits. Interpretation of the measured and 3D TCAD simulated single-event upset (SEU) responses of bulk planar circuits and bulk FinFET circuits using the short-time based upset criteria quantitatively explains the observed divergence of low-LET FinFET cross sections from simple geometric scaling predictions. Comparisons of measured and computed single-event cross section responses show excellent agreement.

Impact of recombination on heavy ion induced single event upset cross-section

The experimental dependence of the single event upset (SEU) cross-section versus linear energy transfer (LET) function in the nanoscale (with feature size less than 100 nm) memories is explained with the proposed recombination-limited charge yield, which is significantly dependent on LET.

Failure rate calculation method for high power devices in space applications at low earth orbit

This paper discusses the universal calculation method for space proton induced failure rate on high power device. High energetic particles can be the reason of power device failure in both terrestrial and space. T-CAD simulation result gives a threshold charge value for the device destruction which is triggered by energetic proton from space. The amount of threshold charge depends on applied voltage for high power device. The probability of charge generation in silicon due to proton penetration is considered as well. This probability function variation depends on the thickness of device and incident energy of proton which studied before at there. Last consideration on this paper is 3.3kV PiN diode's Single Event Upset Cross section and failure rate which was calculated by proposed method in Low earth orbit environment condition.

A Quantitative Analysis of DICE SRAM SEU Caused by Heavy Ion Elastic Scattering

A 4 Mbit DICE latch SRAM exhibits single event upset(SEU) cross-section of $10^{14}$ – $10^{12}~\mathrm {cm}^{2}/\mathrm {bit}$ in vertically incident heavy-ion beam tests. TCAD simulations show that the DICE latch works, and that the SEU is not caused by charge sharing. Numerical simulations on particle elastic collision gives quantitative evidence that it is caused by elastic scattering between the incident ion and target nucleus. Three scenarios of elastic scattering SEU are calculated separately in order to get a deeper understanding. The upset cross-section’s dependencies on ion energy, incident angle and the distance between DICE nodes are analyzed. A designing suggestion that paired nodes of DICE latch should be at least $6~\mu \mathrm {m}$ away is firstly presented.

Semi-Empirical Method for Estimation of Single-Event Upset Cross Section for SRAM DICE Cells

We propose a new semi-empirical method for estimation of Single Event Upset (SEU) cross section for SRAM Dual Interlocked Cells (DICE) with known distance between neighboring sensitive volumes. The method is based on experimental analysis of SEU maps in sub-100 nm 6T SRAM along with layout considerations and SPICE simulations. This method could help designers to estimate the SEE robustness of DICE cells at the design stage.

Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations

This paper analyzes how body bias and BOX region thickness affect soft error rates in 65-nm SOTB (Silicon on Thin BOX) and 28-nm UTBB (Ultra Thin Body and BOX) FD-SOI processes. Soft errors are induced by alpha-particle and neutron irradiation and the results are then analyzed by Monte Carlo based simulation using PHITS-TCAD. The alpha-particle-induced single event upset (SEU) cross-section and neutron-induced soft error rate (SER) obtained by simulation are consistent with measurement results. We clarify that SERs decreased in response to an increase in the BOX thickness for SOTB while SERs in UTBB are independent of BOX thickness. We also discover SOTB develops a higher tolerance to soft errors when reverse body bias is applied while UTBB become more susceptible

Radiation hardening technology in SOI materials and devices

Based on the great success of silicon material and silicon integrated circuit, the silicon-on-insulator (SOI) technology occurs as a new technology with unique advantages to break the limitation of traditional bulk silicon technology. The existence of the buried oxide (BOX) can fundamentally eliminate the latch-up effect of the bulk CMOS technology. The sensitive volume of charge collection in SOI device is smaller than in bulk one, potentially making SOI devices much more hardened to dose rate effect and single-event upset, the upset cross section is nearly two orders of magnitude smaller. These inherent advantages of SOI technology make it very important in military and space applications. However, the existence of the thick buried oxide also makes the total ionizing dose (TID) effect of the SOI devices more complicated. The radiation-induced trapped charge in the buried oxide can lead to serious degradations of the SOI devices and circuits in the space and nuclear radiation environment, such as the increases of the off-state leakage current in the partially-depleted devices and the decreases of the front-gate threshold voltage in the fully-depleted NMOS devices. Meanwhile, the relatively thick field oxide is also very soft to ionizing radiation. Two common types of field oxide isolation are local oxidation of silicon (LOCOS) and shallow trench isolation (STI). LOCOS isolation has been replaced by STI to reduce spacing between adjacent devices in the advanced submicron technology node. STI induced leakage after TID radiation has become a dramatic problem in modern technologies. Both the STI oxide and the buried oxide can potentially impact the total dose tolerance in SOI transistors. This limits the application of SOI technology in radiation hardening. It is only by solving the problem of the total dose hardening that the SOI technology can better fulfill its military applications. In addition, the single-event effect and dose rate effect of the SOI circuits become more complicated due to the less critical charge for upset, higher operating frequency and enhanced parasitic bipolar effect for the deep submicron technology. All these factors challenge the hardening design technique of the SOI devices and circuits. In this paper, the difference of ionizing radiation effects between bulk-silicon devices and SOI devices is compared. In order to enhance the radiation hardness of single event effect and dose rate effect in SOI device, the method of suppressing the parasitic bipolar transistor effect is proposed. Furthermore, the radiation hardened methods for TID effect in SOI technology is investigated from two levels: radiation hardened by material and process, radiation hardened by layout. The development of an independent SOI radiation hardening technology will contribute to solve the problem in military electronics, such as radiation hardening, high reliability, and to promote the sustainable development of national defense construction and national security.

Multiple cell upset cross-section modeling: A possible interpretation for the role of the ion energy-loss straggling and Auger recombination

We found that the energy deposition fluctuations in the sensitive volumes may cause the multiple cell upset (MCU) multiplicity scatter in the nanoscale (with feature sizes less than 100nm) memories. A microdosimetric model of the MCU cross-section dependence on LET is proposed. It was shown that ideally a staircase-shaped cross-section vs LET curve spreads due to the energy-loss straggling impact into a quasi-linear dependence with a slope depending on the memory cell area, the cell critical energy and efficiency of charge collection. This paper also presents a new model of the Auger recombination as a limiting process of the electron–hole charge yield, especially at the high-LET ion impact. A modified form of the MCU cross-section vs LET data interpolation is proposed, discussed and validated.

Single event upsets sensitivity of low energy proton in nanometer static random access memory

Low-energy protons are able to generate enough energy through direct ionization to cause a high single event upset cross section as the feature size of semiconductor devices shrinks. It poses a large challenge on the present proton single event modeling test technique and the space upset rate prediction method. Experimental study of proton single event effect in three different feature sizes of static random access memory (SRAM) (i.e. 65 nm, 90 nm, and 250 nm) is carried out based on domestic low-energy proton accelerators and also the foreign middle-high proton accelerators. Complete cross section curves of proton single event upset from low energy to high energy are acquired. Test results show that single event upset cross section below 1 MeV proton is up to three orders of magnitude higher than the saturation cross section of high-energy proton in nanometer SRAM. However, single event upset is not observed for protons below 3 MeV in 250 nm SRAM, and no single event multiple-cell upsets occur for protons below 1 MeV in 90 nm and 65 nm SRAM. The accurate geometrical structure model of composite sensitive volume is constructed through the combination of test data with device information, and calibrated further by single event test data of low-LET heavy ion and high-energy proton. Simulation results based on the model and Monte-Carlo calculation can reveal the root cause of low-proton single event upset cross section peak. Proton single event upsets are only caused through direct ionization of protons below 1 MeV. When low-energy protons pass through the multiple metallization and passivation layers of the device, the energy spectrum is broadened near the Bragg peak of the proton direct ionization, and the energy is deposited concentratedly into the sensitive volume through direct ionization. When the proton energy is too high or too low, the energy can not be deposited effectively into the sensitive volume through direct ionization. The energy spectrum straggling of low-energy protons due to the use of degrader has a large influence on the height and width of the single event upset cross section peak. Moreover, the contribution of low protons to the space proton single event upset rate is predicted for GEO orbit environment in the worst day environment. It shows that the direct ionization from low energy dominates the proton single event upset rate in the space in 65 nm SRAM. With the development of device technology, the critical charge of single event upset will be further reduced; and to the single event upset from low proton direct ionization more attention must be paid in the study and evaluation of single event effect.

Energy and angular dependence of single event upsets in ESA SEU Monitor

The new generation ESA SEU Monitor is first applied to beam verification of Beijing HI-13 Tandem accelerator according to the popularization need of Europe Space Agency and at the desire of contrast of domestic acceleraor with international accelerator. Heavy ion single event cross section of ESA SEU Monitor obtained at HI-13 is compared with those from European facilities. Beam homogeneity is also analyzed based on the SEU physical bitmap. The accuracy of heavy ion beam monitoring technique at HI-13 accelerator is verified. Through combining the heavy ion testing result with the data from the other test sites, it can be observed that the differences between SEU cross sections with different heavy ion energies of the same LET value can reach 1-3 orders of magnitude in the sub-threshold zone of single event upset cross section curve below the direct ionization LET threshold. The geometrical structure, critical charge and collection efficiency of sensitive volume are constructed on the basis of testing data and process information. The physical mechanism of energy effect on single event upsets in ESA SEU Monitor is revealed through using the Monte-Carlo calculation. Nuclear reactions between incident heavy ions and material atoms can account for single event upsets below the direct ionization LET threshold. The differences in nuclear reaction type and cross section between the diferent energy heavy ions and material atoms are the root cause of the difference among heavy ion SEU cross sections with different energies at the same LET value. On the other hand, SEU bitmap nonuniformity among different blocks in memory array and different orientation dices in ESA SEU Monitor is first reported when the heavy ion is incident at a tilting angle at the low LET value. The analysis of device layout and calculation verification can account for this phenomenon. The material of interlayer dielectric with the tilting ion passing through is different when heavy ion reaches the sensitive volume of memory blocks with different data. This leads to the difference between efficient LET values inside the sensitive volume for different data blocks. Eventually the sensitivity difference in single event upset among blocks with different data occures. The applications of ESA SEU Monitor in beam calibrating, tuning of domestic accelerator and single event effect test can be broadened further. Prediction method of space single event upset rate including heavy ion energy dependence and special angular dependence based on full-physical simulation should be developed in the future.

Proton Cross-Sections from Heavy-Ion Data in Deep-Submicron Technologies

This paper reports on the calculation of proton SEU cross section from heavy-ion data using a number of different models. Model accuracy is checked using data on proton and heavy-ion cross sections from the published literature. The closed-form models developed with earlier semiconductor devices typically overestimated the proton cross section, and the difference increased with smaller feature sizes. The results emphasize that low LET heavy-ion data is crucial in determining the proton upset cross section.

Circuit Simulation Based Validation of Flip-Flop Robustness to Multiple Node Charge Collection

In modern scaled process technologies a single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate. Consequently, hardening flip-flops to transients at the data and control inputs, as well as to single event upsets, due to either single or multi-node upsets is increasingly important. This paper presents a circuit simulation based methodology for pre-layout hardness validation to multi-node upsets. The methodology is applied to the development of a lower power and area radiation hardened flip-flop design, as well as a number of previous hardened flip-flops. Comparison of the hardness, as measured by estimated upset cross-section, is also facilitated. The results also show the importance of specific circuit design aspects to achieving hardness. One of the comparisons to prior designs includes a comparison of the cross-section as determined by the proposed circuit simulation methodology to ion beam results.

Analysis of Hamming EDAC SRAMs Using Simplified Birthday Statistics

In 2009 Tausch developed a simple equation to predict the cumulative probability of a single uncorrectable (double bit) error occurring within Hamming protected memory as the number of random upsets increase. This paper furthers that work by: 1) developing a simplified equation that predicts the number of failing addresses vs. random upsets in Hamming protected memories, 2) showing the range over which this simplified equation matches more complicated, 3) proving the validity of this equation through radiation testing, 4) showing how this equation can be used to improve test techniques in various simulator environments and 5) showing how this equation can be used to better analyze test results and to understand and predict the behavior of Hamming memories in radiation environments. An approach will be described to better calculate upset cross-sections of Hamming protected SRAMs in heavy ion environments.

Flip-flops soft error rate evaluation approach considering internal single-event transient

The internal single-event transient (SET) induced upset in flip-flops is becoming significant with the increase of the operating frequency. However, the conventional soft error rate (SER) evaluation approach could only produce an approximate upset prediction result caused by the internal SET. In this paper, we propose an improved SER evaluation approach based on Monte Carlo simulation. A novel SET-based upset model is implemented in the proposed evaluation approach to accurately predict upsets caused by the internal SET. A test chip was fabricated in a commercial 65 nm bulk process to validate the accuracy of the improved SER evaluation approach. The predicted single-event upset cross-sections are consistent with the experimental data.