Upset Cross Section Research Articles

SEU Prediction From SET Modeling Using Multi-Node Collection in Bulk Transistors and SRAMs Down to the 65 nm Technology Node

A new methodology of prediction for SEU is proposed based on SET modeling. The modeling of multi-node charge collection is performed using the ADDICT model for predicting single event transients and upsets in bulk transistors and SRAMs down to 65 nm. The predicted single event upset cross sections agree well with experimental data for SRAMs.

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

Neutron- and proton-induced single-event upset cross sections of D- and DICE-Flip/Flops are analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton testing of the flip/flops show only a 30%-50% difference between D- and DICE-Flip/Flop error rates and cross sections. Simulations are used to show that charge sharing is the primary cause for the similar failures-in-time (FIT) rates. Such small improvement in the single-event performance of the DICE implementation over standard D-Flip/Flop designs may warrant careful consideration for the use of DICE designs in 40 nm bulk technologies and beyond.

First principles simulation technique for characterizing single event effects

This paper develops a new simulation technique to characterize single event effects on semiconductor devices. The technique used to calculate the single event effects is developed according to the physical interaction mechanism of a single event effect. An application of the first principles simulation technique is performed to predict the ground-test single event upset effect on field-programmable gate arrays based on 0.25 μm advanced complementary metal—oxide—semiconductor technology. The agreement between the single event upset cross section accessed from a broad-beam heavy ion experiment and simulation shows that the simulation technique could be used to characterize the single event effects induced by heavy ions on a semiconductor device.

Impact of Technology Scaling on the Heavy-Ion Upset Cross Section of Multi-Level Floating Gate Cells

The corruption of the information stored in floating gate cells due to heavy-ion strikes is a critical issue for the use of Flash memories in space. In this work we examine how feature size scaling affects the single event upset sensitivity of multi-level floating gate cells with NAND architecture. Both experimental data on heavy-ion irradiation and analytical modeling are used to study how the threshold LET and saturation cross section depend on the cell feature size. A comparison is also carried out between multi-level and single-level floating gate cells.

静态单粒子翻转截面的获取及分类

静态单粒子翻转截面的获取及分类

Single-Event Upset (SEU) Results of Embedded Error Detect and Correct Enabled Block Random Access Memory (Block RAM) Within the Xilinx XQR5VFX130

Recent heavy ion measurements of the single-event upset (SEU) cross section for 65 nm embedded block random access memory (Block RAM) are presented. Results of initial investigation into the on-chip Error Detection and Correction (EDAC) are also discussed.

Single Event Transient Hardness of a New Complementary (npn <formula formulatype="inline"><tex Notation="TeX">$+$</tex></formula> pnp) SiGe HBT Technology on Thick-Film SOI

We report heavy-ion microbeam and total dose data for a new complementary (npn + pnp) SiGe on thick-film SOI technology. Measured transient waveforms from heavy-ion strikes indicate a significantly shortened single-event-induced transient current, while maintaining the total dose robustness associated with SiGe devices. Heavy-ion broad-beam data confirm a reduced single event upset (SEU) cross-section in a high-speed shift register circuit.

Increase in the Heavy-Ion Upset Cross Section of Floating Gate Cells Previously Exposed to TID

Electronic chips working in the space environment are constantly subject to both single event and total ionizing dose effects. To emulate this scenario for Flash memories, we tested under heavy ions floating gate cells, previously irradiated with x-rays, without performing any erase and program operation in between the two exposures. We observed an increase in the heavy-ion upset cross section in the devices that were submitted to TID irradiations, especially at low LETs. This effect is attributed to the combination of the threshold voltage shifts induced by heavy ions and x-rays. Implications for the hardness assurance of Flash memories are discussed.

Effects of Scaling in SEE and TID Response of High Density NAND Flash Memories

Heavy ion single-event effect (SEE) measurements and total ionizing dose (TID) response for Micron Technology single-level cell 1, 2, 4, 8 Gb commercial NAND flash memory and multi-level cell 8, 16, 32 Gb are reported. The heavy ion measurements were extended down to LET 0.1 MeV-cm2/mg. Scaling effects in SEE and TID response are discussed. Floating gate bit error upset cross section does not scale with feature size at high LETs, except for single-level cell 8 Gb device which is built with 51 nm processes. The threshold LET does not change with scaling. Charge pump TID degradation and standby current improves with scaling. In general, the effect of radiation is either unchanged or is less severe for highly scaled NAND flash memories.

Impact of total dose on heavy-ion upsets in floating gate arrays

We studied the impact of previous X-ray irradiation on the sensitivity of floating gate cells to heavy-ion upsets, to emulate the concurrent occurrence of both total ionizing dose and single event effects in the space environment. An increasing heavy-ion upset cross section for increasing total dose was measured, especially with low-LET particles, where the enhancement can be bigger than one order of magnitude. We attributed this behaviour to the combination of the threshold voltage shifts induced by X-rays and heavy ions.

Heavy-Ion-Induced Digital Single Event Transients in a 180 nm Fully Depleted SOI Process

Heavy- ion-induced single events transients (SETs) in advanced digital circuits are a significant reliability issue for space-based systems. SET pulse widths in silicon-on-insulator (SOI) technologies are often significantly shorter than those in comparable bulk technologies. In this paper, heavy-ion-induced digital single-event transient measurements are presented for a 180-nm fully depleted SOI technology. Upset cross-sections for this technology with and without body-ties are analyzed using 3-D TCAD simulations. Pulse broadening is shown to lengthen the measured SET pulse widths significantly for the circuit without body contacts.

Pulsed Laser SEU Cross Section Measurement Using Coincidence Detectors

Pulsed laser testing is a useful technique for an accurate inspection of potential weak zones in a layout of an integrated circuit. A laser pulse can provoke a similar effect as a particle hitting with the advantage of a perfect location of the hitting point. The present work describes a general method to determine a Pulsed Laser Single Event Upset (SEU) Cross Section over digital circuits by means of counting statistics. The technique is based on a coincidence detector that counts fault events by comparing synchronous outputs of the digital circuit under test and a replica of the design running on a control FPGA. A correspondence map, previously generated by injection fault analysis techniques on the replica, establishes a one-way correspondence between output patterns and each bit flip. With this scheme, the SEU is detected dynamically just using a comparison between the running model and the circuit.

Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process

In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error cross section is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal spacing as a mitigation technique shows an order of magnitude decrease on upset cross section as compared to a conventional layout, and the use of guard-rings show no noticeable effect on upset cross section.

Three-dimensional numerial simulation of single event upset effects in static random access memory

Three-Dimensional model of static random access memory （SRAM） six-transistor cell is generated by three dimensional process simulator FLOOPS, and device simulator DESSIS is used to simulate the single-event upset effect in SRAM. Single-event upset and charge collecting maps are calculated directly from 3-D simulations. Single event upset maps and cross-section curves obtained from numerial simulation show excellent agreement with broad beam cross section curves and micro-beam upset images for 2 kbit hardened SRAM. It indicates that the three-dimensional model could be used to research the single event upsets in SRAM.

Low Energy Proton Single-Event-Upset Test Results on 65 nm SOI SRAM

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.

Integrating Circuit Level Simulation and Monte-Carlo Radiation Transport Code for Single Event Upset Analysis in SEU Hardened Circuitry

Monte-Carlo radiation transport code is coupled with SPICE circuit level simulation to identify regions of single event upset vulnerability in an SEU hardened flip-flop, as well as predict single event upset cross sections and on-orbit soft error rates under static and dynamic operating conditions.

Using Subthreshold Heavy Ion Upset Cross Section to Calculate Proton Sensitivity

This paper reports on SEU proton calculations using the very low LET heavy ion upset cross section measurements. This approach allows for improving the prediction of the proton sensivity of devices based on heavy ion data.

The Effect of Active Delay Element Resistance on Limiting Heavy Ion SEU Upset Cross-Sections of SOI ADE/SRAMs

This paper discusses the effective limiting heavy-ion induced single-event upset cross section of radiation-hardened 150 nm SOI SRAM and the resistance of the active-delay element (ADE) used in the memory cell. The effective limiting upset cross-section of ADE/SRAM is found to be proportional to the product of the limiting upset cross-section of the 6T SRAM of the same CMOS technology and a dimensionless function of the normalized ADE resistance. In addition, a cross-section higher than this effective limiting cross-section at high effective LET (>250 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg) is observed. This additional contribution to the cross-section is attributed to the upset caused by the high effective LET heavy ion hitting the on-transistor in the memory cell.

Heavy Ion Induced Upset Cross-Sections of 150nm SOI CMOS SRAMs Fabricated in UNIBOND

This paper discusses the heavy ion performance of the 150nm SOI CMOS SRAMs with hardened active delay element in the feedback path. The limiting upset cross-section is found to be related to the average resistance of the delay element.

Proton Induced Single Event Upset in 6 T SOI SRAMs

This paper presents a method to estimate the saturated proton upset cross section for 6 T SOI SRAM cells from layout and technology parameters. The calculated proton upset cross section based on this method is in good agreement with test results for our 6 T SOI SRAM cells processed using 0.15 and 0.35 mum technologies