Radiation hardening technology in SOI materials and devices

Abstract

Based on the great success of silicon material and silicon integrated circuit, the silicon-on-insulator (SOI) technology occurs as a new technology with unique advantages to break the limitation of traditional bulk silicon technology. The existence of the buried oxide (BOX) can fundamentally eliminate the latch-up effect of the bulk CMOS technology. The sensitive volume of charge collection in SOI device is smaller than in bulk one, potentially making SOI devices much more hardened to dose rate effect and single-event upset, the upset cross section is nearly two orders of magnitude smaller. These inherent advantages of SOI technology make it very important in military and space applications. However, the existence of the thick buried oxide also makes the total ionizing dose (TID) effect of the SOI devices more complicated. The radiation-induced trapped charge in the buried oxide can lead to serious degradations of the SOI devices and circuits in the space and nuclear radiation environment, such as the increases of the off-state leakage current in the partially-depleted devices and the decreases of the front-gate threshold voltage in the fully-depleted NMOS devices. Meanwhile, the relatively thick field oxide is also very soft to ionizing radiation. Two common types of field oxide isolation are local oxidation of silicon (LOCOS) and shallow trench isolation (STI). LOCOS isolation has been replaced by STI to reduce spacing between adjacent devices in the advanced submicron technology node. STI induced leakage after TID radiation has become a dramatic problem in modern technologies. Both the STI oxide and the buried oxide can potentially impact the total dose tolerance in SOI transistors. This limits the application of SOI technology in radiation hardening. It is only by solving the problem of the total dose hardening that the SOI technology can better fulfill its military applications. In addition, the single-event effect and dose rate effect of the SOI circuits become more complicated due to the less critical charge for upset, higher operating frequency and enhanced parasitic bipolar effect for the deep submicron technology. All these factors challenge the hardening design technique of the SOI devices and circuits. In this paper, the difference of ionizing radiation effects between bulk-silicon devices and SOI devices is compared. In order to enhance the radiation hardness of single event effect and dose rate effect in SOI device, the method of suppressing the parasitic bipolar transistor effect is proposed. Furthermore, the radiation hardened methods for TID effect in SOI technology is investigated from two levels: radiation hardened by material and process, radiation hardened by layout. The development of an independent SOI radiation hardening technology will contribute to solve the problem in military electronics, such as radiation hardening, high reliability, and to promote the sustainable development of national defense construction and national security.